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IS24C16A-2GLI Datasheet(PDF) 5 Page - Integrated Silicon Solution, Inc

Part # IS24C16A-2GLI
Description  1K-bit/2K-bit/4K-bit/8K-bit/16K-bit 2-WIRE SERIAL CMOS EEPROM
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS24C16A-2GLI Datasheet(HTML) 5 Page - Integrated Silicon Solution, Inc

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
5
Rev. F
01/09/06
IS24C02A
IS24C04A
IS24C08A
IS24C16A
ISSI®
Page Write
The IS24C02A/04A/08A/16A is capable of 16-byte Page-
Write operation. A Page-Write is initiated in the same manner
as a Byte Write, but instead of terminating the internal Write
cycle after the first data word is transferred, the Master
device can transmit up to 15 more bytes. After the receipt of
each data word, the EEPROM responds immediately with an
ACK on SDA line, and the four lower order data word address
bits are internally incremented by one, while the higher order
bits of the data word address remain constant. If a byte
address is incremented from the last byte of a page, it
returns to the first byte of that page. If the Master device
should transmit more than 16 bytes prior to issuing the Stop
condition,theaddresscounterwill“rollover,”andthepreviously
written data will be overwritten. Once all 16 bytes are
received and the Stop condition has been sent by the Master,
the internal programming cycle begins. At this point, all
received data is written to the IS24C02A/04A/08A/16A in a
single Write cycle. All inputs are disabled until completion of
the internal Write cycle.
Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage of
the typical Write cycle time. Once the Stop condition is
issued to indicate the end of the host's Write operation, the
IS24C02A/04A/08A/16A initiates the internal Write cycle.
ACK polling can be initiated immediately. This involves
issuing the Start condition followed by the Slave address for
a Write operation. If the EEPROM is still busy with the Write
operation, no ACK will be returned. If the IS24C02A/04A/
08A/16A has completed the Write operation, an ACK will be
returned and the host can then proceed with the next Read
or Write operation.
WRITE OPERATION
Byte Write
In the Byte Write mode, the Master device sends the Start
condition and the Slave address information (with the R/
W
set to Zero) to the Slave device. After the Slave generates
an ACK, the Master sends the byte address that is to be
written into the address pointer of the IS24C02A/04A/08A/
16A. After receiving another ACK from the Slave, the
Master device transmits the data byte to be written into the
address memory location. The IS24C02A/04A/08A/16A
acknowledges once more and the Master generates the
Stop condition, at which time the device begins its internal
programming cycle. While this internal cycle is in progress,
the device will not respond to any request from the Master
device.
DEVICE ADDRESSING
The Master begins a transmission by sending a Start
condition. The Master then sends the address of the
particular Slave devices it is requesting. The Slave device
(Fig. 5) address is 8 bits.
The four most significant bits of the Slave address are fixed
as 1010 for the IS2402A/04A/08A/16A.
The next three bits of the Slave address are specific for
each of the EEPROM. The bit values enable access to
multiple memory blocks or multiple devices.
The IS24C02A uses the three bits A0, A1, and A2 in a
comparison with the hard-wired input values on the A0, A1,
and A2 pins. Up to eight IS24C02A units may share the 2-
wire bus.
The IS24C04A uses the bit B0 to address either the upper
or the lower 256 byte block in the device. Also, the bits A1
and A2 are used in a comparison with the hard-wired input
values on the A1 and A2 pins. Up to four IS24C04A units
may share the 2-wire bus.
The IS24C08A uses the bits B0 and B1 to address one of
the four 256 byte blocks in the device. Also, the bit A2 is
used in a comparison with the hard-wired input value on the
A2 pin. Up to two IS24C08A units may share the 2-wire
bus.
The IS24C16A uses the bits B0, B1, and B2 to address one
of the eight 256 byte blocks in the device.
The last bit of the Slave address specifies whether a Read
or Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a Write
operation is selected.
After the Master transmits the Start condition and Slave
address byte (Fig. 5), the appropriate 2-wire Slave
(eg.IS24C02A/04A/08A/16A) will respond with ACK on the
SDA line. The Slave will pull down the SDA on the ninth
clock cycle, signaling that it received the eight bits of data.
The selected EEPROM then prepares for a Read or Write
operation by monitoring the bus.


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