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IS24C128A-2WLI Datasheet(PDF) 4 Page - Integrated Silicon Solution, Inc

Part # IS24C128A-2WLI
Description  128K-bit/ 256K-bit 2-WIRE SERIAL CMOS EEPROM
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS24C128A-2WLI Datasheet(HTML) 4 Page - Integrated Silicon Solution, Inc

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCEDINFORMATION
Rev. 00B
06/27/06
ISSI®
IS24C128A
IS24C256A
DEVICE OPERATION
The IS24C128A/256A features a serial communication and
supports a bi-directional 2-wire bus transmission protocol
called I2CTM.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and
a Serial Clock line (SCL). The protocol defines any device
that sends data onto the SDA bus as a transmitter, and the
receiving devices as receivers. The bus is controlled by
Master device which generates the SCL, controls the bus
access and generates the Stop and Start conditions. The
IS24C128A/256A is the Slave device on the bus.
The Bus Protocol:
– Data transfer may be initiated only when the bus is not
busy
– During a data transfer, the SDA line must remain stable
whenever the SCL line is high. Any changes in the data
line while the SCL line is high will be interpreted as a
Start or Stop condition.
The state of the SDA line represents valid data after a Start
condition. The SDA line must be stable for the duration of
the High period of the clock signal. The data on the SDA
line may be changed during the Low period of the clock
signal. There is one clock pulse per bit of data. Each data
transfer is initiated with a Start condition and terminated
with a Stop condition.
Start Condition
The Start condition precedes all commands to the device
and is defined as a High to Low transition of SDA when
SCL is High. The IS24C128A/256A monitors the SDA and
SCL lines and will not respond until the Start condition is
met.
Stop Condition
The Stop condition is defined as a Low to High transition of
SDA when SCL is High. All operations must end with a Stop
condition.
Acknowledge (ACK)
After a successful data transfer, each receiving device is
required to generate an ACK. The Acknowledging device
pulls down the SDA line.
Reset
The IS24C128A/256A contains a reset function in case
the 2-wire bus transmission is accidentally interrupted
(eg. a power loss), or needs to be terminated mid-stream.
The reset is caused when the Master device creates a
Start condition. To do this, it may be necessary for the
Master device to monitor the SDA line while cycling the
SCL up to nine times. (For each clock signal transition to
High, the Master checks for a High level on SDA.)
Standby Mode
Power consumption is reduced in standby mode. The
IS24C128A/256A will enter standby mode: a) At Power-up,
and remain in it until SCL or SDA toggles; b) Following the
Stop signal if no write operation is initiated; or c) Following
any internal write operation
DEVICE ADDRESSING
The Master begins a transmission by sending a Start
condition. The Master then sends the address of the
particular Slave devices it is requesting. The Slave device
(Fig. 5) address is 8 bits.
The four most significant bits of the Slave device address
are fixed as 1010 for the IS24C128A/256A.
This device has three address bits (A2, A1, and A0),
which allows up to eight IS24C128A/256A devices to
share the 2-wire bus. Upon receiving the Slave address,
the device compares the three address bits with the
hardwired A2, A1, and A0 input pins to determine if it is
the appropriate Slave.
The last bit of the Slave address specifies whether a Read
or Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
After the Master transmits the Start condition and Slave
address byte (Fig. 5), the appropriate 2-wire Slave (eg.
IS24C128A/256A) will respond with ACK on the SDA
line. The Slave will pull down the SDA on the ninth clock
cycle, signaling that it received the eight bits of data.
The selected IS24C128A/256A then prepares for a Read
or Write operation by monitoring the bus.
WRITE OPERATION
Byte Write
In the Byte Write mode, the Master device sends the Start
condition and the Slave address information (with the R/
W
set to Zero) to the Slave device. After the Slave generates
an ACK, the Master sends the two byte address that are to
be written into the address pointer of the IS24C128A/
256A. After receiving another ACK from the Slave, the
Master device transmits the data byte to be written into the
address memory location. The IS24C128A/256A
acknowledges once more and the Master generates the
Stop condition, at which time the device begins its internal
programming cycle. While this internal cycle is in progress,
the device will not respond to any request from the Master
device.


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