Read Mode

The DS2030 executes a read cycle whenever WE (write

enable) is inactive (high) and CE (chip enable) is active

(low). The unique address specified by the 15 address

inputs (A0 to A14) defines which of the 32,768 bytes of

data is to be accessed. Valid data will be available to the

the last address input signal is stable, providing that CE

and OE (output enable) access times are also satisfied.

If CE and OE access times are not satisfied, then data

access must be measured from the later occurring sig-

Write Mode

The DS2030 executes a write cycle whenever the CE

and WE signals are active (low) after address inputs

are stable. The later-occurring falling edge of CE or WE

will determine the start of the write cycle. The write

cycle is terminated by the earlier rising edge of CE or

WE. All address inputs must be kept valid throughout

the write cycle. WE must return to the high state for a

be initiated. The OE control signal should be kept inac-

tive (high) during write cycles to avoid bus contention.

However, if the output drivers have been enabled (CE

from its falling edge.

Data-Retention Mode

The DS2030AB provides full functional capability for

greater than 4.5V and write-protects at 4.25V. Data is

support circuitry. The NV static RAM constantly moni-

SRAM automatically write-protects itself. All inputs

become “don’t care”, and all data outputs become high

energy source to the RAM to retain data. During power-

nects the lithium energy source. Normal RAM operation

Battery Charging

charges the battery. The UL-approved charger circuit

includes short-circuit protection and a temperature-sta-

bilized voltage reference for on-demand charging of

the internal battery. Typical data-retention expectations

A maximum of 96 hours of charging time is required to

fully charge a depleted battery.

System Power Monitoring

out-of-tolerance trip point, the output RST is forced

active (low). Once active, the RST is held active until

tery. On power-up, the RST output is held active until

the external supply is greater than the selected trip

SRAM is ready for access by the microprocessor.

Freshness Seal and Shipping

The DS2030 is shipped from Dallas Semiconductor with

the lithium battery electrically disconnected, guarantee-

ing that no battery capacity has been consumed during

transit or storage. As shipped, the lithium battery is

~60% charged, and no preassembly charging opera-

tions should be attempted.

the lithium battery is enabled for backup operation. A

96 hour initial battery charge time is recommended for

new system installations.

DS2030Y/AB Single-Piece 256kb

Nonvolatile SRAM

10

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Memory Operation Truth Table

X = Don’t care.

WE

CE

OE

MODE

OUTPUTS

100

Read

Active

Active

101

Read

Active

High Impedance

00

XWrite

Active

High Impedance

X1

X

Standby

Standby

High Impedance