Integrated Circuit Solution Inc.

9

LPSR017-0A 09/13/2001

IC62LV1024AL

IC62LV1024ALL

WRITE CYCLE NO. 2 (

CE1

CE1

CE1

CE1

HIGH-Z

DATA UNDEFINED

DATA-IN VALID

ADDRESS

DIN

CE1

CE2

WE

DOUT

Notes:

1. The internal write time is defined by the overlap of

CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the

rising or falling edge of the signal that terminates the Write.

2. I/O will assume the High-Z state if

DATA RETENTION SWITCHING CHARACTERISTICS

Symbol

Parameter

TestCondition

Min.

Max.

Unit

Vcc for Data Retention

See Data Retention Waveform

2.0

3.3

V

Data Retention Current

Vcc = 2.0V,

CE1

≥ Vcc – 0.2V

Com. (-L)

—

30

µA

Com. (-LL)

—

5

µA

Ind. (-L)

—

50

µA

Ind. (-LL)

—

10

µA

Data Retention Setup Time

See Data Retention Waveform

0

—

ns

Recovery Time

See Data Retention Waveform

—ns

DATA RETENTION WAVEFORM (

CE1

CE1

CE1

CE1

CE1 Controlled)

CE1

CE1

GND

3.0V

2.2V

Data Retention Mode