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IC62LV5128LL-70T Datasheet(PDF) 8 Page - Integrated Circuit Solution Inc |
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IC62LV5128LL-70T Datasheet(HTML) 8 Page - Integrated Circuit Solution Inc |
8 / 11 page 8 Integrated Circuit Solution Inc. LPSR012-0B 08/31/2001 IC62LV5128L IC62LV5128LL - 55 - 70 - 100 Symbol Parameter Min. Max. Min. Max. Min. Max Unit tWC Write Cycle Time 55 — 70 — 100 — ns tSCE CE to Write End 50 — 65 — 80 — ns tAW Address Setup Time to Write End 50 — 65 — 80 — ns tHA Address Hold from Write End 0 — 0 — 0 — ns tSA Address Setup Time 0 — 0 — 0 — ns tPWE WE Pulse Width 40 — 40 — 80 — ns tSD Data Setup to Write End 25 — 30 — 40 — ns tHD Data Hold from Write End 0 — 0 — 0 — ns tHZWE(3) WE LOW to High-Z Output — 30 — 30 — 40 ns tLZWE(3) WE HIGH to Low-Z Output 5 — 5 — 5 — ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range, Standard and Low Power) DATA-IN VALID DATA UNDEFINED tWC tSCE tAW tHA tPWE tHZWE HIGH-Z tLZWE tSA tSD tHD ADDRESS CE WE DOUT DIN AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled) |
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