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Integrated Circuit Solution Inc.

LPSR014-0C 1/22/2003

IC62LV51216L

IC62LV51216LL

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

DESCRIPTION

The

8.388,608 bit static RAMs organized as 524,288 words by 16

bits. They are fabricated using

technology. This highly reliable process coupled with innova-

tive circuit design techniques, yields high-performance and

low power consumption devices.

When CE1 is HIGH or when CE2 is low (deselected) or both LB

and UB are HIGH, the device assumes a standby mode at

which the power dissipation can be reduced by using CMOS

input levels.

Easy memory expansion is provided by using Chip Enable

Output and Enable inputs, CE1, CE2 and OE. The active LOW

Write Enable (WE) controls both writing and reading of the

memory. A data byte allows Upper Byte (UB) and Lower Byte

(LB) access.

The IC62LV51216L and IC62LV51216LL are packaged in the

JEDEC standare 44-pin TSOP-2 and 48-pin 8*10mm TF-BGA.

FUNCTIONAL BLOCK DIAGRAM

512K x 16 LOW VOLTAGE, ULTRA

LOW POWER CMOS STATIC RAM

FEATURES

• High-speed access times: 55, 70, 100 ns

• CMOS low power operation

• TTL compatible interface levels

• Single 2.7V-3.6V Vcc power supply

• Fully static operation: no clock or refresh re-

quired

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

• Available in the know good die from 44-pin

TSOP-2 and 48-pin 8x10mm TF-BGA

• CE2 pin only for 48-pin TF-BGA.

A0-A18

CE1/ CE2

OE

WE

512K x 16

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

UB

LB