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IC89C52A-24W Datasheet(PDF) 8 Page - Integrated Circuit Solution Inc |
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IC89C52A-24W Datasheet(HTML) 8 Page - Integrated Circuit Solution Inc |
8 / 22 page IC89C52(51)A 8 Integrated CircuitSolution Inc. MC008-0C 11/27/2001 Flash Command Definitions Bus First Bus Cycle Second Bus Cycle Cycle Operation Address Data VPP Operation Address Data VPP Normal Verify (1) (n+1) (2) P2.6 X 00H H P2.7 Low SA (3) SD (3) H Read Signature Byte 4 P2.6 X 90H H P2.7 Low 30H D5H 31H 52H 32H 55H/AAH Program Code Memory 2 P2.6 X 40H H PROG PA (3) PD (3) 12V/H Program Verify (1) (n+1) (2) P2.6 X C0H H P2.7 Low SA PVD (3) H Program Lock Bit 1 2 P2.6 X 60H H PROG X D0H 12V/H Program Lock Bit 2 2 P2.6 X 70H H PROG X D0H 12V/H Program Lock Bit 3 2 P2.6 X 80H H PROG X D0H 12V/H Chip Erase 2 P2.6 X 20H H PROG X D0H 12V/H Erase Verify (1) (n+1) (2) P2.6 X A0H H P2.7 Low EA (3) EVD (3) H Note: 1. Normal Verify: Internal flash sense amplifier uses the same threshold as instruction executing threshold. Program Verify: The flash sense amplifier applies an internally generated higher margin voltage to the addressed byte. If a comparison between the programmed byte and the true data is successful, there is a margin exists in the programmed data. Erase Verify: The flash sense amplifier applies an internally generated lower margin voltage to the addressed byte. Reading FFH from the addressed byte indicates that all bits in the bytes are erased. 2. To verify n bytes data. 3. SA = Selected Address of memory location to be read except program or erase verify. SD = Data read from location SA with Normal Verification threshold. PA = Address of memory location to be programmed. PD = Data to be programmed at location PA. PVD = Data read from location PA during program verify. EA = Address of memory location to be read during erase verify. EVD - Data read from location EA during erase verify. Programming Core Memory Every code byte in the Flash array can be written and the entire array can be erased using the appropriate command from Port 0 by programmer or application system. The program/erase are two-cycle operations. The first cycle is command write cycle; the command 40H is written by P2.6 falling and rising edges. The command would be held a stable value within P2.6 low state. The command decoder enables programming flag after the first cycle is completion, then the internal programming flag is set. Rising edge of PROG will clear internal programming flag, so the programming command must be presented every programming cycle. The second cycle is real flash programming cycle. The programming address and data are latched at PROG falling edge, the programming time is controlled by low time of PROG. The programming flag is cleared at PROG rising edge in the second cycle. Programming address range is from 0 to 1FFFH. IC89C52(51)A programming range is from 0 to 1FFFH, but the program counter will jump to external menory while MCU executing the address is excess 0FFFH. The IC89C52(51)A code memory programming now is described in Figure 6. |
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