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IC62LV12816L-100BI Datasheet(PDF) 7 Page - Integrated Circuit Solution Inc |
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IC62LV12816L-100BI Datasheet(HTML) 7 Page - Integrated Circuit Solution Inc |
7 / 10 page Integrated Circuit Solution Inc. 7 LPSR011-0B 06/06/2001 IC62LV12816L IC62LV12816LL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) -55 -70 -100 Symbol Parameter Min. Max. Min. Max. Min. Max Unit tWC Write Cycle Time 55 70 100 ns tSCE CE to Write End 50 65 80 ns tAW Address Setup Time to Write End 50 65 80 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Setup Time 0 0 0 ns tPWB LB, UB Valid to End of Write 45 60 80 ns tPWE" WE Pulse Width 40 40 80 ns tSD Data Setup to Write End 25 30 40 ns tHD Data Hold from Write End 0 0 0 ns tHZWE! WE LOW to High-Z Output 30 30 40 ns tLZWE! WE HIGH to Low-Z Output 5 5 5 ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V and output loading specified in .igure 1. 2. The internal write time is defined by the overlap of CE LOW, and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 3. Tested with the load in .igure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 4. Tested with OE HIGH DATA UNDEFINED t WC VALID ADDRESS t SCS t PWE1 t PWE2 t AW t HA HIGH-Z t PWB t HD t SA t HZWE ADDRESS CS UB, LB WE DOUT DIN DATAIN VALID t LZWE t SD AC WAVE.ORMS WRITE CYCLE NO. 1(1,2) (CS, Controlled, OE = HIGH or LOW) Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CS) [ ( LB) = (UB) ] (WE). |
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