Integrated Circuit Solution Inc.

9

LPSR015-0A 1/3/2002

IC62LV1008L

IC62LV1008LL

Notes:

1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and

WE LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the

rising or falling edge of the signal that terminates the Write.

2. I/O will assume the HIGH-z state if

HIGH-Z

DATA UNDEFINED

DATA-IN VALID

ADDRESS

DIN

CE1

CE2

WE

DOUT