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IC62VV5128L-55B Datasheet(PDF) 2 Page - Integrated Circuit Solution Inc |
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IC62VV5128L-55B Datasheet(HTML) 2 Page - Integrated Circuit Solution Inc |
2 / 11 page 2 Integrated Circuit Solution Inc. LPSR020-0A 11/26/2001 IC62VV5128L IC62VV5128LL ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. DESCRIPTION The ICSI IC62VV5128L and IC62VV5128LL is a low voltage, 524,288 words by 8 bits, CMOS SRAM. It is fabricated using ICSI's low voltage, six transistor (6T), CMOS technology. The device is targeted to satisfy the demands of the state-of-the-art technologies such as cell phones and pagers. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Additionally, easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable ( WE) controls both writing and reading of the memory. The IC62VV5128L and IC62VV5128LL are available in 32-pin 8*20mm TSOP-1, 8*13.4mm TSOP-1 and 48-pin 6*8mm TF- BGA. FUNCTIONAL BLOCK DIAGRAM A0-A18 CE OE WE 512K x 8 MEMORY ARRAY DECODER COLUMN I/O CONTROL CIRCUIT GND VCC I/O DATA CIRCUIT I/O0-I/O7 512K x 8 1.8V and LOW VCC CMOS STATIC RAM FEATURES • Access times of 55, 70, 100 ns • CMOS Low power operation: ICC1=10mA (typical)* operation ISB2=1µA (typical)* standby * Typical values are measured at VCC=1. 8V, TA=25°C • Low data retention voltage: 1.0V (min.) • Output Enable ( OE) and Chip Enable ( CE) inputs for ease in applications • TTL compatible inputs and outputs • Fully static operation: — No clock or refresh reguired • Single 1.65V-2.2V power supply • Available in the 32-pin 8*20mm TSOP- 1, 32-pin 8*13.4mm TSOP-1 and 48- pin 6*8mm TF-BGA |
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