6

Integrated Circuit Solution Inc.

LPSR015-0A 1/3/2001

IC62LV1008L

IC62LV1008LL

-55

-70

-100

Symbol Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Read Cycle Time

55

—

70

—

100

—

ns

Address Access Time

—

55

—

70

—

100

ns

Output Hold Time

10

—

10

—

15

—

ns

CE1 Access Time

—

55

—

70

—

100

ns

CE2 Access Time

—

55

—

70

—

100

ns

OE Access Time

—

30

—

35

—

50

ns

OE to Low-Z Output

5

—

5

—

5

—

ns

—

20

0

25

0

30

ns

10

—

10

—

10

—

ns

10

—

10

—

10

—

ns

0

20

0

25

0

30

ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 2.2V and output

loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

AC TEST CONDITIONS

Parameter

Unit

Input Pulse Level

0.4V to 2.2V

Input Rise and Fall Times

5 ns

Input Reference Level

1.3V

Output Reference Level

1.5V

Output Load

See Figures 1 and 2

AC TEST LOADS

Figure 1

Figure 2

5 pF

Including

jig and

scope

OUTPUT

1 TTL

100 pF

Including

jig and

scope

OUTPUT

1 TTL