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MB82D01171A-85L Datasheet(PDF) 10 Page - Fujitsu Component Limited. |
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MB82D01171A-85L Datasheet(HTML) 10 Page - Fujitsu Component Limited. |
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10 / 27 page  MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 10 (2) Write Operation *1: Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR) . *2: New write address is valid from either CE1 or WE is brought to High. *3: Maximum value is applicable if CE1 is kept at Low and both WE and OE are kept at High. *4: The tOEH is specified from end of tWC (Min) and is a reference value when access time is determined by tOE. If actual value is shorter than specified minimum value, tOE become longer by the amount of subtracting actual value from specified minimum value. *5: The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1 stays Low. *6: tOHCL (Min) must be satisfied if read operation is not performed prior to write operation. In case OE is disabled after tOHCL (Min) , WE Low must be asserted after tRC (Min) from CE1 Low. In other words, read operation is initiated if tOHCL (Min) is not satisfied. *7: Applicable if CE1 stays Low after read operation. *8: tCW and tWP is applicable if write operation is initiated by CE1 and WE, respectively. *9: tWRC and tWR is applicable if write operation is terminated by CE1 and WE, respectively. The tWR (Min) can be ignored if CE1 is brought to High together or after WE is brought to High. In such case, the tCP (Min) must be satisfied. Parameter Symbol -80/-80L/ -80LL -85/-85L/ -85LL -90/-90L/ -90LL Unit Notes Min Max Min Max Min Max Write Cycle Time tWC 90 90 90 ns *1 Address Setup Time tAS 0 0 0 ns *2 Address Hold Time tAH 45 45 45 ns *2 CE1 Write Setup Time tCS 0 1000 0 1000 0 1000 ns CE1 Write Hold Time tCH 0 1000 0 1000 0 1000 ns WE Setup Time tWS 0 0 0 ns WE Hold Time tWH 0 0 0 ns LB and UB Setup Time tBS −5 −5 −5 ns LB and UB Hold Time tBH −5 −5 −5 ns OE Setup Time tOES 0 1000 0 1000 0 1000 ns *3 OE Hold Time tOEH 45 1000 45 1000 45 1000 ns *3, *4 tOEH[ABS] 20 20 20 ns *5 OE High to CE1 Low Setup Time tOHCL −3 −3 −3 ns *6 Address Hold Time to OE High tOHAH 0 0 0 ns *7 CE1 Write Pulse Width tCW 60 60 60 ns *1, *8 WE Write Pulse Width tWP 60 60 60 ns *1, *8 CE1 Write Recovery Time tWRC 15 15 15 ns *1, *9 WE Write Recovery Time tWR 15 1000 15 1000 15 1000 ns *1, *3, *9 Data Setup Time tDS 20 20 20 ns Data Hold Time tDH 0 0 0 ns CE1 High Pulse Width tCP 20 20 20 ns *9 |
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