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Data Sheet
PT7A4410/4410L
T1/E1/OC3 System Synchronizer
PT0106(09/02)
Ver:0
7
Functional Description
Overall Operation
The PT7A4410/4410L is a multitrunk synchronizer that pro-
vides the clock and frame signals for T1 and E1 primary rate
digital transmission links, and STS-3/OC3 links.
It basically consists of the Clock Generator, Mode/State Con-
trol Machine, Time Interval Error (TIE) Corrector, Digital Phase-
Locked Loop (DPLL), Analog Phase- Locked Loop (APLL),
Input Impairment Monitor and Output Interface Circuit.
The DPLL circuit provides synchronization of the output sig-
nals with any given input reference signal, and the TIE circuit
ensures phase continuity whenever the input reference signal
source is changed.
Referring to the block diagram on Page 3, the detailed func-
tions of the PT7A4410/4410L are described as follows.
Master Clock
The PT7A4410/4410L uses either an external clock source or
an external crystal and a few discrete components with its
internal oscillator as the master clock.
Reference Select MUX
The PT7A4410/4410L accepts two independent reference sig-
nals, the primary reference and secondary reference. Either
one of them is selected by the Reference Select MUX circuit
and sent to the TIE circuit. The selection is decided according
to the availability and quality of the reference signals, the
mode operation, and State. Refer to Tables 3, 6 and 7.
Feedback Frequency Select MUX
The feedback frequency is selected by FS1 and FS2 (as shown
in Table 3) to match the particular incoming reference fre-
quency (1.544MHz, 2.048MHz or 8kHz). A reset (RST) must
be performed after every frequency select input change.
Table 3. Feedback Frequency Selection
Time Interval Error (TIE) Corrector
The purpose of the TIE corrector is to allow the phase of the
output signals to be constant while switching between two
mutually incoherent reference signal input sources. Whenever
a new input reference signal is selected, the TIE corrector mea-
sures the phase difference between it and the feedback signal
and aligns them using a variable delay circuit. Thus, the TIE
Corrector output a virtual reference input signal for the DPLL
that has the same phase as it had for the previous reference
signal input source. Thus, the PT7A4410/4410L provides a
totally seamless (“glitch-free”) transition from one reference
signal to another. The TIE Corrector diagram is shown in Fig-
ure 3.
2
S
F2
S
F 2
S
F 2
S
F2
S
F1
S
F1
S
F 1
S
F 1
S
F1
S
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8
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z
H
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4
4
5
.
1
11
z
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8
4
0
.
2
Figure 3. TIE Corrector
Comparing
Circuit
Programmable
Delay
Circuit
PRI or SEC
From
Select MUX
Delay Value
Virtual Reference
Signal
To DPLL
Feedback Signal
From
Frequency Select MUX
TCLR
TIE Corrector Enable
From
Mode/State Machine
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