MOTOROLA

MC68322 PRODUCT INFORMATION

7

GRAPHICS EXECUTION UNIT (GEU)

The GEU is comprised of two independent processing units, the RGP and the PVC. The GEU performs all

graphics functions required by complex PDLs. One of these functions is the bit-block transfer (BitBLT). The

MC68322 performs extremely fast BitBLT operations. One, two, and three operand BitBLT operations are

supported yielding 256 logical BitBLT operation combinations. The MC68322 also provides flexibility,

through control registers, to provide many configurations. These control registers provide printer video

characteristics (such as margins, width, and height), system memory timing, wait states, access auto

termination, DRAM control, and external device access control.

GEU OPERATION

The RGP and PVC perform burst read and write accesses to DRAM through the DRAM controller. The RGP

interprets a display list, which the EC000 Core or host application generates, to render a banded bit map

page image. After a page image (or band image) is rendered by the RGP, the PVC converts the bitmap

image into a serial data stream and transfers the rendered page image through the video interface to the

print engine. The software interfaces to the RGP and PVC employ a combination of resources, including

MC68322 registers and interrupts. The RGP and PVC require only a minimal amount of initialization and

intervention by the EC000 Core to produce a banded page image and to transfer the image to the print

engine. A functional block diagram depicting the GEU operations of the MC68322 is illustrated in Figure 3.

MC68322

EC000

CORE

GRAPHICS

EXECUTION UNIT (GEU)

PRINT ENGINE

DRAM

DISPLAY

LIST

BAND1

BAND0

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PROM

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DRAM

CONTROL

RISC GRAPHICS

PROCESSOR (RGP)

PRINT ENGINE VIDEO

CONTROLLER (PVC)

Figure 3. MC68322 Functional Block Diagram

RISC GRAPHICS PROCESSOR (RGP)

The RGP is a high-performance bit-image processor optimized for the 16-bit DRAM interface on the

MC68322. The RGP achieves performance levels that enable the MC68322 to be used effectively in

banding applications or in other high-speed or high-density bit-mapped graphics products. The RGP is

comprised of several major blocks: graphic order parser, graphic order execution unit, write back logic and

band control registers. The software interface to the RGP consists of three registers: RGP start register

(RSR), RGP diagnostic register (RDR), and the RGP interrupt event register (RIER).

The RGP is activated when the EC000 Core writes the starting address of a display list into the RSR. A

display list is a list of special instructions called graphic orders. The RGP executes these graphic orders to

Freescale Semiconductor, Inc.

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