7

ATSTK94

2309B–FPSLI–01/02

RS232-compatible

UARTs

The RS232-compatible UARTs allow for communication between the two on-board

UARTs through the null-modem cable. It is also possible for communication between

the UARTs and other devices, such as your PC, by using a simple terminal program.

UART Connections

The 2 UART connections, see Table 6, are made to DB9 connectors. Printf commands

are sent out on UART 0.

Multiple Clocks

There are multiple clock circuits on the Starter Kit. A Manual Clock or the 4 MHz Oscilla-

tor are connected to 2 of the FPGA Global Clock pins. The 32,768 KHz (for the

implementation of the Real Time Clock calculations), 4 MHz, or 18.432 MHz can be

used to drive the AVR. The FPGA has 8 Global Clocks, 2 of these (GCLK5 and GCLK6)

can also be driven from the AVR system Clock. GCLK6 can alternatively be driven from

the Watchdog timer or one of the timer counters. For full details on the Clock circuits in

the FPSLIC device please refer to the AT94K datasheet available on the Atmel web site,

at http://www.atmel.com/atmel/acrobat/doc1138.pdf.

Table 6. UART Connections

UART

Source /Destination

Pin

Hardware Settings

UART 0

RX0

140

Connect Cable to UART0

UART 0

TX0

141

Connect Cable to UART 0

UART1

RX1

149

Connect Cable to UART 1

UART1

TX1

150

Connect Cable to UART 1

Table 7. Clock Connections

Frequency

Destination

Pin

Hardware Settings

Manual Clock

FPGA GCLK7

162

Use MAN CLK Switch (SW9)

to Pulse Clock

Available Global

Clocks

FPGA GCLK1

FPGA GCLK2

FPGA GCLK3

FPGA GCLK4

FPGA GCLK7

FPGA GCLK8

4

47

57

100

162

204

32,768 KHz Crystal

AVR TOSC 1

147

None

4 MHz Oscillator

AVR System Clock

138

For Rev2 – JP17 towards side of

board, JP18 is unconnected.

For Rev3 and beyond –Position of

JP17 is changed, it is aligned with

FPGA and AVR jumpers. JP17 is

connected towards the inner side of

the board, JP18 is unconnected.

18.432 MHz Crystal

AVR System Clock

138

For Rev2 – JP17 towards middle of

board, JP18 connected.

For Rev3 and beyond – Position of

JP17 is changed, it is aligned with

FPGA and AVR jumpers. JP17 is

connected towards the edge of the

board, JP18 is connected.