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SP000069400 Datasheet(PDF) 5 Page - Infineon Technologies AG |
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SP000069400 Datasheet(HTML) 5 Page - Infineon Technologies AG |
5 / 31 page TLE 6251 G Final Data Sheet 5 Rev. 3.2, 2006-04-05 Pin Configuration Figure 1 Pin Configuration (top view) Table 1 Pin Definitions and Functions Pin No. Symbol Function 1TxD CAN transmit data input; 20 k Ω pull-up, LOW in dominant state 2 GND Ground 3 V CC 5 V supply input; block to GND with 100 nF ceramic capacitor 4RxD CAN receive data output; LOW in dominant state, push-pull output stage 5 V µC Logic voltage level adapter input; connect to pin V CC for 5 V microcontroller, connect to additional supply voltage for other logic voltage levels, block to GND with 100 nF ceramic capacitor 6EN Mode control input 1; internal pull-down, see Figure 6 7INH Control output; set HIGH to activate voltage regulator; open drain 8NERR Diagnosis output 1; error and power on indication output, push-pull output stage 9WK Wake-up input; bi-level sensitive AEP03398.VSD 7 6 5 4 3 2 1 TxD GND V CC RxD V µC EN INH 8 9 10 11 12 13 14 CANH CANL SPLIT WK NERR NSTB V S TLE 6251 G (P-DSO-14-13) |
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