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ZMD44101 Datasheet(PDF) 6 Page - Zentrum Mikroelektronik Dresden AG |
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ZMD44101 Datasheet(HTML) 6 Page - Zentrum Mikroelektronik Dresden AG |
6 / 26 page ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver PRELIMINARY - March 2005 Copyright © 2005, ZMD AG Page 6 of 26 Digital Core TX FIFO 128x8 RX FIFO 256x8 Inter- face SPI Paral- lel Reg. Bank MISO MOSI SCK SS ALE RD WR DA[7:0] IRQ GPD SPIconfig[5:0] SPItx[7:0] SPIstart SPIrx[7:0] 4 Interfaces 4.1 Overview Figure 4-1: Interface Block Diagram The ZMD44101 provides a parallel interface and an SPI to access the internal register bank, the TX and the RX FIFO. Additionally it has a IRQ output and a dedicated global power down (GPD) input. By default both interfaces the parallel and the SPI as slave are available. For proper operation the unused interface shall be disabled. The parallel interface is disabled by setting RD,WR, and ALE to high, putting the DataAddress[7:0] bus into High-Z state. The SPI is disabled by setting SS to high. The SPI can also be configured as master. In the master setup is behaves like a remote interface which can be controlled by the external microcontroller via the ZMD44101 parallel interface and some SPI control register in the register bank. |
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