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MAX6391KA23-T Datasheet(PDF) 5 Page - Maxim Integrated Products

Part # MAX6391KA23-T
Description  Dual-Voltage uP Supervisory Circuits with Sequenced Reset Outputs
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX6391KA23-T Datasheet(HTML) 5 Page - Maxim Integrated Products

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Dual-Voltage µP Supervisory Circuits
with Sequenced Reset Outputs
_______________________________________________________________________________________
5
Pin Description
PIN
MAX6391
MAX6392
NAME
FUNCTION
11
RESET IN2
Input Voltage for RESET2 Monitor. High-impedance input for internal reset
comparator. Connect this pin to an external resistive-divider network to set the reset
threshold voltage.
22
VCC
Supply Voltage and Input Voltage for Primary Supply Monitor
3
3
CSRT
RESET2 Delay Set Capacitor. Connect to VCC for a fixed 140ms (min) timeout period
or to an external capacitor for a user-adjustable timeout period after VCC exceeds its
minimum threshold.
4
4
GND
Ground
55
RESET2
Secondary Reset Output, Open-Drain, Active-Low. RESET2 changes from high to low
when either VCC or RESET IN2 drop below their thresholds. RESET2 remains low for a
user-adjustable timeout period (see CSRT) or a fixed 140ms (min) after VCC and
RESET IN2 meet their minimum thresholds.
66
R2
47k
Ω Internal Pullup Resistor for RESET2. Connect to external voltage for RESET2
high pullup.
77
RESET1
Primary Reset Output, Open-Drain (MAX6391) or Push-Pull (MAX6392), Active-Low.
RESET1 changes from HIGH to LOW when the VCC input drops below the selected
reset threshold. RESET1 remains LOW for the reset timeout period after VCC exceeds
the minimum threshold.
8—
R1
47k
Ω Internal Pullup Resistor for RESET1. Connect to external voltage for RESET1
high pullup.
—8
MR
Manual Reset, Active-Low, Internal 47k
Ω Pullup to VCC. Pull LOW to force a reset.
RESET1 and RESET2 remain asserted as long as MR is LOW and for the RESET1 and
RESET2 timeout periods after MR goes HIGH. Leave unconnected or connect to VCC
if unused.
Detailed Description
Each device includes a pair of voltage monitors with
sequenced reset outputs. The first block monitors VCC
only (RESET1 output is independent of the RESET IN2
monitor). It asserts a reset signal (LOW) whenever VCC
is below the preset voltage threshold. RESET1 remains
asserted for at least 140ms after VCC rises above the
reset threshold. RESET1 timing is internally set in each
device. VCC voltage thresholds are available from
1.57V to 4.63V. In all cases VCC acts as the master
supply (all resets are asserted when VCC goes below
its selected threshold). The VCC input also acts as the
device power supply.
The second block monitors both RESET IN2 and VCC. It
asserts a reset signal (LOW) whenever RESET IN2 is
below the 625mV threshold or VCC is below its reset
threshold. RESET2 remains asserted for a fixed 140ms
(min) or a user-adjustable time period after RESET IN2
rises above the 625mV reset threshold and RESET1 is
deasserted. Resets are guaranteed valid for VCC down
to 1V.
The timing diagram in Figure 2 shows the reset timing
characteristics of the MAX6391/MAX6392. As shown in
Figure 2, RESET1 deasserts 140ms (min) (tRP1) after
VCC exceeds the reset threshold. RESET2 deasserts
tRP2 (140ms minimum or a user-adjustable timeout peri-
od) after RESET IN2 exceeds 625mV and RESET1 is
deasserted. When RESET IN2 drops below 625mV
while VCC is above the reset threshold, RESET2 asserts
within 10µs typ. RESET1 is unaffected when this hap-
pens. When VCC falls below VTH1, RESET2 always
asserts before RESET1 (tRD2 < tRD1).


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