TLK3104SA

QUAD 3.125 Gbps SERIAL TRANSCEIVER

SCAS651B-– AUGUST 2000 – REVISED SEPTEMBER 2001

7

POST OFFICE BOX 655303

detailed description (continued)

10 Gbps ethernet transceiver modes

When CODE is high, the TLK3104SA supports the 32-bit data path, 4-bit control, 10 gigabit media independent

interface (XGMII) and full encoding scheme currently proposed in the IEEE 802.3ae 10 gigabit ethernet task

force. In these modes, the TLK3104SA performs the serialization/deserialization and channel synchronization

function of an extended auxiliary unit interface (XAUI) also currently proposed in the IEEE 802.3ae 10 gigabit

ethernet task force.

The TLK3104SA is intended as a prestandard XAUI transceiver. The device supports most of the functions

defined in clause 47 and 48 of the IEEE 802.3ae proposed 10 gigabit ethernet draft 2.0 standard. However,

some functions that have been included in the current draft of the standard are not currently supported in the

TLK3104SA. These are:

frequency between the reference clock and the incoming serial data as defined in P802.3ae D2.0 clause 48.

for bit and channel alignment on the XAUI interface as defined in P802.3ae D2.0 clause 48.

the XGMII or report faults as 0xFE as defined in P802.3ae D2.0 clause 46.

extensions for the management data input/output interface as defined in P802.3ae D2.0 clause 45.

the XGMII as defined in P802.3ae D2.0 clause 46.

parallel interface clocking

There are two clocking choices selectable via the PSYNC pin detailed in Table 2. Under channel sync mode

(PSYNC = high), TCA is used as the transmit data clock for all four channels. Under independent channel mode

(PSYNC = low), each channel uses its own transmit data clock (TCA–TCD) to latch data into the TLK3104SA.

A data FIFO is placed in the transmit data path to resolve any phase difference between the transmit data clocks

and differential reference clock, RFCP/N.

Table 2. Parallel Interface Clocking Modes

PSYNC

PARALLEL INTERFACE CLOCKING OPERATION

Low

Independent channel mode. TC[A–D]/RC[A–D] are used to clock in/out each individual channel.

High

Channel sync mode. TCA/RCA are used to clock in/out all channels of data.

On the receive data path, in independent channel mode, the data for each channel is output referenced to each

channel’s extracted receive clock. In channel sync mode, the data on all channels are synchronized and output

referenced to the extracted receive clock for channel A, RCA. A FIFO is enabled in the parallel receive data path

on each channel to compensate for channel skew and clock phase tolerance differences between the recovered

clocks for each channel and the receive output clock, RCA. This FIFO has a total depth of eleven bytes.

parallel interface data

There are two data mode choices selectable via the CODE pin detailed in Table 3. In SERDES mode, the

transmit data bus for each channel accepts 10-bit wide 8-B/10-B encoded data at the TDx[0..9] pins. Data is

latched on the rising and falling edge of the transmit data clock. The 8-B/10-B encoded data is then phase

aligned to the reference clock (RFCP/RFCN), serialized, then transmitted sequentially beginning with bit 0

(TDx0) over the differential high-speed serial transmit pins.