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DS2480B Datasheet(PDF) 10 Page - Dallas Semiconductor |
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DS2480B Datasheet(HTML) 10 Page - Dallas Semiconductor |
10 / 30 page DS2480B 10 of 30 101999 The type of time slot b2 (write 1 or write 0) is determined by the DS2480B as follows: b2 = rn if conflict (as chosen by the host) = b0 if no conflict (there is no alternative) = 1 if error (there is no response) The response the host will receive during a complete pass through a Search ROM function using the Search Accelerator consists of 16 bytes as follows: first byte 7 6 5 4 3 2 1 0 r’3 d3 r’2 d2 r’1 d1 r’0 d0 et cetera 16 th byte 7 6 5 4 3 2 1 0 r’63 d63 r’62 d62 r’61 d61 r’60 d60 As before, the index (values from 0 to 63, “n”) designates the position of the bit in the ROM ID of a MicroLAN compatible device. The character “d” marks the discrepancy flag in that particular bit position. The discrepancy flag will be 1 if there is a conflict, or no response in that particular bit position, and 0 otherwise. The character “r” marks the actually chosen path at that particular bit position. The chosen path is identical to b2 for the particular bit position of the ROM ID. To perform a Search ROM sequence one starts with all bits rn being 0s. In case of a bus error, all subsequent response bits r’n are 1s until the Search Accelerator is deactivated. Thus, if r’63 and d63 are both 1, an error has occurred during the search procedure and the last sequence has to be repeated. Otherwise r’n (n = 0 ... 63) is the ROM code of the device that has been found and addressed. For the next Search ROM sequence one reuses the previous set rn (n = 0 ... 63) but sets rm to 1 with “m” being the index number of the highest discrepancy flag (that is, 1) and sets all ri to 0 with i > m. This process is repeated until the highest discrepancy occurs in the same bit position for two consecutive passes. The table below shows an example for the communication between host and DS2480B to perform one pass through the Search ROM function using the Search Accelerator. After a device has been identified and addressed, a memory function (not specified here) is executed and finally a reset pulse is generated. This example assumes that the DS2480B was in Command Mode and that regular 1–Wire speed is used. |
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