CY7C4205-15JC datasheet(7/25 Pages) CYPRESS

Part #	CY7C4205-15JC

Description	64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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7 / 25 page

CY7C4425/4205/4215

CY7C4225/4235/4245

7

Notes:

14. .tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the

rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK edge.

15. The clocks (RCLK, WCLK) can be free-running during reset.

16. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.

Switching Waveforms (continued)

Read Cycle Timing

tCLKH

tCLKL

NO OPERATION

tSKEW2

WEN

tCLK

tOHZ

tREF

RCLK

Q0 –Q17

EF

REN

WCLK

OE

tOE

tENS

tOLZ

tA

tENH

VALID DATA

42X5–7

[14]

tRS

tRSR

Q0- Q17

RS

tRSF

OE=1

OE=0

REN, WEN,

LD

EF,PAE

FF,PAF,

HF

42X5–8

Reset Timing[15]

[16]

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