Philips Semiconductors

Product specification

74ALVCH162827

20-bit buffer/line driver, non-inverting, with 30

Ω

termination resistors (3-State)

2

1998 Sep 29

853-2127 20100

FEATURES

and ground bounce

DESCRIPTION

The 74ALVCH162827 high-performance CMOS device combines

low static and dynamic power dissipation with high speed and high

output drive.

The 74ALVCH162827 20-bit buffers provide high performance bus

interface buffering for wide data/address paths or buses carrying

parity. They have NAND Output Enables (nOE1, nOE2) for

maximum control flexibility.

The 74ALVCH162827 is designed with 30

Ω series resistance in both

the pull-up and pull-down output structures. This design reduces line

noise in applications such as memory address drivers, clock drivers

and bus receivers/transmitters.

To ensure the high impedance state during power up or power

minimum value of the resistor is determined by the

current-sinking/current-sourcing capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data

inputs at a valid logic level.

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

Propagation delay

nAn to nYn

2.9

2.9

ns

Input capacitance

5

pF

Power dissipation capacitance per latch

Output enabled

14

pF

Power dissi ation ca acitance er latch

Output disabled

3

F

NOTES:

1.

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

OUTSIDE NORTH AMERICA

NORTH AMERICA

DWG NUMBER

56-Pin Plastic TSSOP Type II

–40

°C to +85°C

74ALVCH162827DGG

ACH162827DGG

SOT364-1

PIN DESCRIPTION

PIN NUMBER

SYMBOL

FUNCTION

55, 54, 52, 51, 49, 48, 47, 45, 44, 43,

42, 41, 40, 38, 37, 36, 34, 33, 31, 30

1A0 - 1A9

2A0 - 2A9

Data inputs

2, 3, 5, 6, 8, 9, 10, 12, 13, 14,

15, 16, 17, 19, 20, 21, 23, 24, 26, 27

1Y0 - 1Y9

2Y0 - 2Y9

Data outputs

1, 56,

28, 29

1OE1 1OE2,

2OE1, 2OE2

Output enable inputs (active-LOW)

4, 11, 18, 25, 32, 39, 46, 53

GND

Ground (0V)

7, 22, 35, 50

Positive supply voltage