CY7C4821-35AI datasheet(8/23 Pages) CYPRESS

Part #	CY7C4821-35AI

Description	256/512/1K/2K/4K/8K x9 x2 Double Sync FIFOs

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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8 / 23 page

CY7C4801/4811/4821

CY7C4831/4841/4851

Document #: 38-06005 Rev. **

Page 8 of 23

Notes:

12. The clocks (RCLKA,RCLKB, WCLKA,WCLKB) can be free-running during reset.

13. After reset, the outputs will be LOW if (OEA,OEB) = 0 and three-state if (OEA,OEB)=1.

14. Holding (WENA2/LDA,WENB2/LDB) HIGH during reset will make the pin act as a second enable pin. Holding(WENA2/LDA,WENB2/LDB) LOW during reset will make the

pin act as a load enable for the programmable flag offset registers.

Switching Waveforms (continued)

Reset Timing

tRS

tRSR

QA0−QA8

RSA(RSB)

tRSF

OEA(OEB)=1

OEA(OEB)=0

RENA1, RENA2

(RENB1,RENB2)

EFA, PAEA

FFA, PAFA

48X1–8

tRSS

tRSR

tRSS

tRSR

tRSS

WENA2/LDA

WENA1

(WENB1)

(WENB2/LDB)

(EFB, PAEB)

(FFB, PAFB)

(QB0−QB8)

[12]

[13]

[14]

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