CY7C1372BV25
CY7C1370BV25
Document #: 38-05252 Rev. **
Page 8 of 26
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
Notes:
Notes:
7.
All Voltage referenced to Ground.
8.
Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot: VIL(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
9.
tCS and tCH refer to the set-up and hold time requirements of latching data
from the boundary scan register.
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Sleep mode
standby current
ZZ > VDD – 0.2V
20
mA
tZZS
Device operation to
ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
Write Cycle Descriptions[8, 8, 9]
Function (CY7C1370BV25)
WE
BWSd
BWSc
BWSb
BWSa
Read
1
XXXX
Write – No bytes written
01111
Write Byte 0 – (DQa and DPa)
01110
Write Byte 1 – (DQb and DPb)
01101
Write Bytes 1, 0
01100
Write Byte 2 – (DQc and DPc)
01011
Write Bytes 2, 0
01010
Write Bytes 2, 1
01001
Write Bytes 2, 1, 0
01000
Write Byte 3 – (DQd and DPd)
00111
Write Bytes 3, 0
00110
Write Bytes 3, 1
00101
Write Bytes 3, 1, 0
00100
Write Bytes 3, 2
00011
Write Bytes 3, 2, 0
00010
Write Bytes 3, 2, 1
00001
Write All Bytes
00000
Function (CY7C1372BV25)
WE
BWSb
BWSa
Read
1
x
x
Write - No Bytes Written
0
1
1
Write Byte 0 - (DQa and DPa)0
1
0
Write Byte 1 - (DQb and DPb)0
0
1
Write Both Bytes
0
0
0