CYP15G0101DXA
PRELIMINARY
Document #: 38-02061 Rev. **
Page 5 of 40
Pin Descriptions
CYP15G0101DXA Single Channel HOTLink II™ Transceiver
Name
I/O Characteristics
Signal Description
Transmit Path Data Signals
TXPER
LVTTL Output,
changes relative to
REFCLK
↑ [1]
Transmit Path Parity Error. Active HIGH. Asserted (HIGH) if parity checking is enabled
(PARCTL
≠ LOW) and a parity error is detected at the Encoder. This output is HIGH for
one transmit character-clock period to indicate detection of a parity error in the character
presented to the Encoder.
If a parity error is detected, the character in error is replaced with a C0.7 character to
force a corresponding bad-character detection at the remote end of the link. This re-
placement takes place regardless of the encoded/non-encoded state of the interface.
This output provides an indication of a Phase-Align Buffer underflow/overflow condition.
When the Phase-Align Buffer is enabled (TXCKSEL
≠ LOW, or TXCKSEL = LOW and
TXRATE = HIGH), and an underflow/overflow condition is detected, TXPER is asserted
and remains asserted until either an atomic Word Sync Sequence is transmitted or
TXRST is sampled LOW to re-center the Phase-Align Buffer.
When BIST is enabled (BISTLE = HIGH) for the transmit channel, BIST progress is
presented on this output. Once every 511 character times (plus a 16-character Word
Sync Sequence when the receive interface is clocked by REFCLK), the TXPER signal
will pulse HIGH for one transmit-character clock period to indicate a complete pass
through the BIST sequence.
TXCT[1:0]
LVTTL Input,
synchronous,
sampled by TXCLK
↑
or REFCLK
↑ [1]
Transmit Control. These inputs are captured on the rising edge of the transmit interface
clock as selected by TXCKSEL, and are passed to the Encoder or Transmit Shifter. They
identify how the TXD[7:0] characters are interpreted. When the Encoder is bypassed,
these inputs are interpreted as data bits. When the Encoder is enabled, these inputs
determine if the TXD[7:0] character is encoded as Data, a Special Character code, or
replaced with other Special Character codes. See Table 1 for details.
TXD[7:0]
LVTTL Input,
synchronous,
sampled by TXCLK
↑
or REFCLK
↑ [1]
Transmit Data Inputs. These inputs are captured on the rising edge of the transmit
interface clock as selected by TXCKSEL, and passed to the Encoder or Transmit Shifter.
When the Encoder is enabled (TXMODE[1:0]
≠ LL), TXD[7:0] specify the specific data
or command character to be sent.
TXOP
LVTTL Input,
synchronous,
internal pull-up,
sampled by
TXCLK
↑ or
REFCLK
↑ [1]
Transmit Path Odd Parity. When parity checking is enabled (PARCTL
≠ LOW), the
parity captured at this input is XORed with the data on the TXD bus to verify the integrity
of the captured character.
TXRST
LVTTL Input, asyn-
chronous,
internal pull-up,
sampled by
TXCLK
↑ or
REFCLK
↑ [1]
Transmit Clock Phase Reset. Active LOW. When sampled LOW, the transmit Phase-
Align Buffer is allowed to adjust its data-transfer timing (relative to TXCLK
↑) to allow
clean transfer of data from the Input Register to the Encoder or Transmit Shift Register.
When TXRST is deasserted (HIGH), the internal phase relationship between TXCLK
↑
and the internal character-rate clock is fixed and the device operates normally.
When configured for half-rate REFCLK sampling of the transmit character stream
(TXCKSEL = LOW and TXRATE = HIGH), assertion of TXRST is only used to clear
Phase-Align Buffer faults caused by highly asymmetric REFCLK periods or REFCLK
inputs with excessive cycle-to-cycle jitter.
During this alignment period, one or more characters may be added to or lost from the
transmit path as the Phase-Align Buffer is cleared or reset.
TXRST must be sampled LOW by a minimum of two consecutive rising edges of TXCLK
(or one REFCLK
↑) to ensure the reset operation is initiated correctly on the channel.
This input is not interpreted when both TXCKSEL and TXRATE are LOW.
Note:
1.
When REFCLK is configured for half-rate operation (TXRATE
= HIGH), this input is sampled (or the outputs change) relative to both the rising and falling
edges of REFCLK.
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