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CY7C1386B
CY7C1387B
Document #: 38-05195 Rev. **
Page 7 of 32
TDO
JTAG serial output
synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of
TCK (BGA only).
TDI
JTAG serial input
synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK (BGA
only).
TMS
Test Mode Select
synchronous
This pin controls the Test Access Port (TAP) state machine. Sampled on the
rising edge of TCK (BGA only).
TCK
JTAG serial
clock
Serial clock to the JTAG circuit (BGA only).
VDD
Power supply
Power supply inputs to the core of the device. Should be connected to
3.3V –5% +10% power supply.
VSS
Ground
Ground for the core of the device. Should be connected to ground of the
system.
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry. Should be connected to a 2.5V –5% or
a 3.3V –5% +10% power supply (see page 20).
VSSQ
I/O Ground
Ground for the I/O circuitry. Should be connected to ground of the system.
NC
–
No connects. Pins are not internally connected.
32M
64M
128M
–
No connects. Reserved for address expansion. Pins are not internally
connected.
Pin Definitions
Name
I/O
Description
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