512K x 36/1M x 18 Pipelined SRAM
with NoBL™ Architecture
CY7C1372BV25
CY7C1370BV25
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05252 Rev. **
Revised April 8, 2002
Features
• Zero Bus Latency, no dead cycles between Write and
Read cycles
• Fast clock speed: 200,167, 150, and 133 MHz
• Fast access time: 3.0, 3.4, 3.8, 4.2 ns
• Internally synchronized registered outputs eliminate
the need to control OE
• Single 2.5V +5%
• Single WE (Read/Write) control pin
• Positive clock-edge triggered, address, data, and
control signal registers for fully pipelined applications
• Interleaved or linear 4-word burst capability
• Individual byte Write (BWSa–BWSd) control (may be
tied LOW)
•CEN pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• JTAG boundary scan for BGA packaging version
• Available in 119-ball bump BGA and 100-pin TQFP
packages
• Automatic power-down available using zz mode or CE
deselect
Functional Description
The CY7C1370BV25 and CY7C1372BV25 SRAMs are
designed to eliminate dead cycles when transitions from
READ to WRITE or vice versa. These SRAMs are optimized
for 100 percent bus utilization and achieves Zero Bus Latency.
They integrate 524,288 × 36 and 1,048,576 × 18 SRAM cells,
respectively, with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. The Cypress
Synchronous Burst SRAM family employs high-speed,
low-power CMOS designs using advanced single layer
polysilicon, threelayer metal technology. Each memory cell
consists of six transistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE1, CE2 and CE3), cycle start input (ADV/LD),
Clock Enable (CEN), Byte Write Selects (BWSa, BWSb, BWSc
and BWSd), and Read-Write control (WE). BWSc and BWSd
apply to CY7C1370BV25 only.
Address and control signals are applied to the SRAM during
one clock cycle, and two cycles later, its associated data
occurs, either Read or Write.
A Clock
Enable
(CEN)
pin
allows
operation
of the
CY7C1370BV25/CY7C1372BV25 to be suspended as long as
necessary. All synchronous inputs are ignored when (CEN) is
HIGH and the internal device registers will hold their previous
values.
There are three Chip Enable (CE1, CE2, CE3) pins that allow
the user to deselect the device when desired. If any one of
these three are not active when ADV/LD is LOW, no new
memory operation can be initiated and any burst cycle in
progress is stopped. However, any pending data transfers
(Read or Write) will be completed. The data bus will be in
high-impedance state two cycles after chip is deselected or a
Write cycle is initiated.
The CY7C1370BV25 and CY7C1372BV25 have an on-chip
two-bit burst counter. In the burst mode, the CY7C1370BV25
and CY7C1372BV25 provide four cycles of data for a single
address presented to the SRAM. The order of the burst
sequence is defined by the MODE input pin. The MODE pin
selects between linear and interleaved burst sequence. The
ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH)
Output Enable (OE) and burst sequence select (MODE) are
the asynchronous signals. OE can be used to disable the
outputs at any given time. ZZ may be tied to LOW if it is not
used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
CLK
Ax
CEN
WE
BWSx
CE
1
CE
CE
2
OE
256K × 36/
MEMORY
ARRAY
Logic Block Diagram
DQx
Data-In REG.
Q
D
CE
CONTROL
and WRITE
LOGIC
3
ADV/LD
Mode
DPx
CY7C1370
CY7C1372
AX
DQX
DPX
BWSX
512K × 18
X = 18:0
X = 19:0
X = a, b, c, d
X = a, b
X = a, b
X = a, b
X = a, b, c, d
X = a, b, c, d
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