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CY7C1367A-150AJC Datasheet(PDF) 6 Page - Cypress Semiconductor

Part # CY7C1367A-150AJC
Description  256K x 36/512K x 18 Pipelined SRAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1367A-150AJC Datasheet(HTML) 6 Page - Cypress Semiconductor

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CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
6
(a) 6P, 7P, 7N, 6N,
6M, 6L, 7L, 6K, 7K,
(b) 7H, 6H, 7G, 6G,
6F, 6E, 7E, 7D, 6D,
(c) 2D, 1D, 1E, 2E,
2F, 1G, 2G, 1H, 2H,
(d) 1K, 2K, 1L, 2L,
2M, 1N, 2N, 1P, 2P
(a) 51, 52, 53, 56,
57, 58, 59, 62, 63
(b) 68, 69, 72, 73,
74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8,
9, 12, 13
(d) 18, 19, 22, 23,
24, 25, 28, 29, 30
DQa
DQb
DQc
DQd
Input/
Output
Data Inputs/Outputs: First Byte is DQa. Second Byte is DQb.
Third Byte is DQc. Fourth Byte is DQd. Input data must meet
set-up and hold times around the rising edge of CLK.
2U
3U
4U
38
39
43
for B and T
version
TMS
TDI
TCK
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. Not available for
TA package version.
5U
42
for B and T
version
TDO
Output
IEEE 1149.1 test output. LVTTL-level output. Not available for
TA package version.
4C, 2J, 4J, 6J, 4R
15, 41,65, 91
VCC
Supply
Core power Supply: +3.3V –5% and +10%
3D, 5D, 3E, 5E, 3F,
5F, 3H, 5H, 3K, 5K,
3M, 5M, 3N, 5N,
3P, 5P
5, 10, 17, 21, 26,
40, 55, 60, 67,
71, 76, 90
VSS
Ground
Ground: GND.
1A, 7A, 1F, 7F, 1J,
7J, 1M, 7M, 1U, 7U
4, 11, 20, 27, 54,
61, 70, 77
VCCQ
I/O Supply
Output Buffer Supply: +2.5V or +3.3V.
1B, 7B, 1C, 7C, 4D,
3J, 5J, 4L, 1R, 5R,
7R, 1T, 2T, 6T, 6U
14, 16, 66
38, 39, 42 for TA
Version
NC
-
No Connect: These signals are not internally connected. User
can leave it floating or connect it to VCC or VSS.
256K X 36 Pin Descriptions (continued)
X36 PBGA Pins
X36 QFP Pins
Name
Type
Description
512K X 18 Pin Descriptions
X18 PBGA Pins
X18 QFP Pins
Name
Type
Description
4P
4N
2A, 3A, 5A, 6A, 3B,
5B, 6B, 2C, 3C, 5C,
6C, 2R, 6R, 2T, 3T,
5T, 6T
37
36
35, 34, 33, 32,
100, 99, 82, 81,
80, 48, 47, 46,
45, 44, 49, 50
92 (T Version)
43 (TA Version)
A0
A1
A
Input-
Synchronous
Addresses: These inputs are registered and must meet the
set-up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and
A1, during burst cycle and wait cycle.
5L
3G
93
94
BWa
BWb
Input-
Synchronous
Byte Write Enables: A byte write enable is LOW for a WRITE
cycle and HIGH for a READ cycle. BWa controls DQa. BWb
controls DQb. Data I/O are high impedance if either of these
inputs are LOW, conditioned by BWE being LOW.
4M
87
BWE
Input-
Synchronous
Write Enable: This active LOW input gates byte write opera-
tions and must meet the set up and hold times around the rising
edge of CLK.
4H
88
GW
Input-
Synchronous
Global Write: This active LOW input allows a full 18-bit WRITE
to occur independent of the BWE and WEn lines and must
meet the set up and hold times around the rising edge of CLK.
4K
89
CLK
Input-
Synchronous
Clock: This signal registers the addresses, data, chip enables,
write control and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around
the clock’s rising edge.
4E
98
CE
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the de-
vice and to gate ADSP.


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