CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
5
256K X 36 Pin Descriptions
X36 PBGA Pins
X36 QFP Pins
Name
Type
Description
4P
4N
2A, 3A, 5A, 6A, 3B,
5B, 6B, 2C, 3C, 5C,
6C, 2R, 6R, 3T, 4T,
5T
37
36
35, 34, 33, 32,
100, 99, 82, 81,
44, 45, 46, 47,
48, 49, 50
92 (T Version)
43 (TA Version)
A0
A1
A
Input-
Synchronous
Addresses: These inputs are registered and must meet the set
up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and
A1, during burst cycle and wait cycle.
5L
5G
3G
3L
93
94
95
96
BWa
BWb
BWc
BWd
Input-
Synchronous
Byte Write: A byte write is LOW for a WRITE cycle and HIGH
for a READ cycle. BWa controls DQa. BWb controls DQb. BWc
controls DQc. BWd controls DQd. Data I/O are high imped-
ance if either of these inputs are LOW, conditioned by BWE
being LOW.
4M
87
BWE
Input-
Synchronous
Write Enable: This active LOW input gates byte write opera-
tions and must meet the set-up and hold times around the
rising edge of CLK.
4H
88
GW
Input-
Synchronous
Global Write: This active LOW input allows a full 36-bit Write
to occur independent of the BWE and BWn lines and must
meet the set-up and hold times around the rising edge of CLK.
4K
89
CLK
Input-
Synchronous
Clock: This signal registers the addresses, data, chip enables,
write control, and burst control inputs on its rising edge. All
synchronous inputs must meet set up and hold times around
the clock’s rising edge.
4E
98
CE
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the de-
vice and to gate ADSP.
2B
97
CE2
Input-
Synchronous
Chip Enable: This active HIGH input is used to enable the de-
vice.
(not available for
PBGA)
92 (for TA
Version only)
CE2
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the de-
vice. Not available for B and T package versions.
4F
86
OE
Input
Output Enable: This active LOW asynchronous input enables
the data output drivers.
4G
83
ADV
Input-
Synchronous
Address Advance: This active LOW input is used to control the
internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
4A
84
ADSP
Input-
Synchronous
Address Status Processor: This active LOW input, along with
CE being LOW, causes a new external address to be regis-
tered and a READ cycle is initiated using the new address.
4B
85
ADSC
Input-
Synchronous
Address Status Controller: This active LOW input causes de-
vice to be deselected or selected along with new external ad-
dress to be registered. A Read or Write cycle is initiated de-
pending upon write control inputs.
3R
31
MODE
Input-
Static
Mode: This input selects the burst sequence. A LOW on this
pin selects Linear Burst. A NC or HIGH on this pin selects
Interleaved Burst.
7T
64
ZZ
Input-
Asynchronous
Snooze: This active HIGH input puts the device in low power
consumption standby mode. For normal operation, this input
has to be either LOW or NC (No Connect).
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