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CY7C1381B
CY7C1383B
Document #: 38-05196 Rev. **
Page 9 of 31
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
ICCZZ
Sleep mode standby current
ZZ < VDD – 0.2V
20
mA
tZZS
Device operation to ZZ
ZZ < VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ
≤ 0.2V
2tCYC
ns
Cycle Descriptions[1, 2, 3]
Next Cycle
Add. Used
ZZ
CE3
CE2
CE1
ADSP
ADSC
ADV
OE
DQ
Write
Unselected
None
0
X
X
1
X
0
X
X
Hi-Z
X
Unselected
None
0
1
X
0
0
X
X
X
Hi-Z
X
Unselected
None
0
X
0
0
0
X
X
X
Hi-Z
X
Unselected
None
0
1
X
0
1
0
X
X
Hi-Z
X
Unselected
None
0
X
0
0
1
0
X
X
Hi-Z
X
Begin Read
External
0010
0
X
X
X
Hi-Z
X
Begin Read
External
0010
1
0
X
X
Hi-Z
Read
Continue Read
Next
0
X
X
X
1
1
0
1
Hi-Z
Read
Continue Read
Next
0
X
X
X
1
1
0
0
DQ
Read
Continue Read
Next
0
X
X
1
X
1
0
1
Hi-Z
Read
Continue Read
Next
0
X
X
1
X
1
0
0
DQ
Read
Suspend Read
Current
0
X
X
X
1
1
1
1
Hi-Z
Read
Suspend Read
Current
0
X
X
X
1
1
1
0
DQ
Read
Suspend Read
Current
0
X
X
1
X
1
1
1
Hi-Z
Read
Suspend Read
Current
0
X
X
1
X
1
1
0
DQ
Read
Begin Write
Current
0
X
X
X
1
1
1
X
Hi-Z
Write
Begin Write
Current
0
X
X
1
X
1
1
X
Hi-Z
Write
Begin Write
External
0010
1
0
X
X
Hi-Z
Write
Continue Write
Next
0
X
X
X
1
1
0
X
Hi-Z
Write
Continue Write
Next
0
X
X
1
X
1
0
X
Hi-Z
Write
Suspend Write
Current
0
X
X
X
1
1
1
X
Hi-Z
Write
Suspend Write
Current
0
X
X
1
X
1
1
X
Hi-Z
Write
ZZ “sleep”
None
1
X
X
X
X
X
X
X
Hi-Z
X
Note:
1.
X = ”Don't Care”, 1 = HIGH, 0 = LOW.
2.
The SRAM always initiates a Read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWx. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state.
OE is a “Don't Care” for the remainder of the Write cycle.
3.
OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle, DQ = High-Z when OE is inactive
or when the device is deselected, and DQ = data when OE is active.
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