9 / 27 page
CY7C1370B
CY7C1372B
Document #: 38-05197 Rev. **
Page 9 of 27
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD – 0.2V
20
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
Write Cycle Descriptions[1, 2]
Function (CY7C1370B)
WE
BWSd
BWSc
BWSb
BWSa
Read
1
X
X
X
X
Write - No bytes written
0
1
1
1
1
Write Byte 0 - (DQa and DPa)
01
11
0
Write Byte 1 - (DQb and DPb)
01
10
1
Write Bytes 1, 0
0
11
00
Write Byte 2 - (DQc and DPc)
01
01
1
Write Bytes 2, 0
0
10
10
Write Bytes 2, 1
0
10
01
Write Bytes 2, 1, 0
0
1
0
0
0
Write Byte 3 - (DQd and DPd)
00
11
1
Write Bytes 3, 0
0
01
10
Write Bytes 3, 1
0
01
01
Write Bytes 3, 1, 0
0
0
1
0
0
Write Bytes 3, 2
0
00
11
Write Bytes 3, 2, 0
0
0
0
1
0
Write Bytes 3, 2, 1
0
0
0
0
1
Write All Bytes
0
0
0
0
0
Function (CY7C1372B)
WE
BWSb
BWSa
Read
1
x
x
Write - No Bytes Written
0
1
1
Write Byte 0 - (DQa and DPa)
0
1
0
Write Byte 1 - (DQb and DPb)
0
0
1
Write Both Bytes
0
0
0