Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

CY7C1363A-117AJC Datasheet(PDF) 10 Page - Cypress Semiconductor

Part # CY7C1363A-117AJC
Description  256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM
Download  26 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1363A-117AJC Datasheet(HTML) 10 Page - Cypress Semiconductor

Back Button CY7C1363A-117AJC Datasheet HTML 6Page - Cypress Semiconductor CY7C1363A-117AJC Datasheet HTML 7Page - Cypress Semiconductor CY7C1363A-117AJC Datasheet HTML 8Page - Cypress Semiconductor CY7C1363A-117AJC Datasheet HTML 9Page - Cypress Semiconductor CY7C1363A-117AJC Datasheet HTML 10Page - Cypress Semiconductor CY7C1363A-117AJC Datasheet HTML 11Page - Cypress Semiconductor CY7C1363A-117AJC Datasheet HTML 12Page - Cypress Semiconductor CY7C1363A-117AJC Datasheet HTML 13Page - Cypress Semiconductor CY7C1363A-117AJC Datasheet HTML 14Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 26 page
background image
CY7C1361A
CY7C1363A
Document #: 38-05259 Rev. *A
Page 10 of 26
TAP Registers
Overview
The various TAP registers are selected (one at a time) via the
sequences of ones and zeros input to the TMS pin as the TCK
is strobed. Each of the TAPs registers are serial shift registers
that capture serial input data on the rising edge of TCK and
push serial data out on subsequent falling edge of TCK. When
a register is selected, it is connected between the TDI and
TDO pins.
Instruction Register
The instruction register holds the instructions that are
executed by the TAP controller when it is moved into the run
test/idle or the various data register states. The instructions
are three bits long. The register can be loaded when it is
placed between the TDI and TDO pins. The parallel outputs of
the instruction register are automatically preloaded with the
IDCODE instruction upon power-up or whenever the controller
is placed in the test-logic reset state. When the TAP controller
is in the Capture-IR state, the two least significant bits of the
serial instruction register are loaded with a binary “01” pattern
to allow for fault isolation of the board-level serial test data
path.
Bypass Register
The bypass register is a single-bit register that can be placed
between TDI and TDO. It allows serial test data to be passed
through the device TAP to another device in the scan chain
with minimum delay. The bypass register is set LOW (V
SS)
when the BYPASS instruction is executed.
Boundary Scan Register
The Boundary Scan register is connected to all the input and
bidirectional I/O pins (not counting the TAP pins) on the device.
This also includes a number of NC pins that are reserved for
future needs. There are a total of 70 bits for the x36 device and
51 bits for the x18 device. The boundary scan register, under
the control of the TAP controller, is loaded with the contents of
the device I/O ring when the controller is in Capture-DR state
and then is placed between the TDI and TDO pins when the
controller is moved to Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE-Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order table describes the order in which
the bits are connected. The first column defines the bit’s
position in the boundary scan register. The MSB of the register
is connected to TDI, and LSB is connected to TDO. The
second column is the signal name, the third column is the
TQFP pin number, and the fourth column is the BGA bump
number.
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device
and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the
instruction register. The register is then placed between the
TDI and TDO pins when the controller is moved into Shift-DR
state. Bit 0 in the register is the LSB and the first to reach TDO
when shifting begins. The code is loaded from a 32-bit on-chip
ROM. It describes various attributes of the device as described
in the Identification Register Definitions table.
TAP Controller Instruction Set
Overview
There are two classes of instructions defined in the IEEE
Standard 1149.1-1990; the standard (public) instructions and
device specific (private) instructions. Some public instructions
are mandatory for IEEE 1149.1 compliance. Optional public
instructions must be implemented in prescribed ways.
Although the TAP controller in this device follows the IEEE
1149.1 conventions, it is not IEEE 1149.1-compliant because
some of the mandatory instructions are not fully implemented.
The TAP on this device may be used to monitor all input and
I/O pads, but can not be used to load address, data, or control
signals into the device or to preload the I/O buffers. In other
words, the device will not perform IEEE 1149.1 EXTEST,
INTEST, or the preload portion of the SAMPLE/PRELOAD
command.
When the TAP controller is placed in Capture-IR state, the two
least significant bits of the instruction register are loaded with
01. When the controller is moved to the Shift-IR state the
instruction is serially loaded through the TDI input (while the
previous contents are shifted out at TDO). For all instructions,
the TAP executes newly loaded instructions only when the
controller is moved to Update-IR state. The TAP instruction
sets for this device are listed in the following tables.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is
to be executed whenever the instruction register is loaded with
all 0s. EXTEST is not implemented in this device.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the device responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between two instruc-
tions. Unlike SAMPLE/PRELOAD instruction, EXTEST places
the device outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the ID register when the controller is in
Capture-DR mode and places the ID register between the TDI
and TDO pins in Shift-DR mode. The IDCODE instruction is
the default instruction loaded in the instruction upon power-up
and at any time the TAP controller is placed in the test-logic
reset state.
SAMPLE-Z
If the High-Z instruction is loaded in the instruction register, all
output pins are forced to a High-Z state and the boundary scan
register is connected between TDI and TDO pins when the
TAP controller is in a Shift-DR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction.
The PRELOAD portion of the command is not implemented in
this device, so the device TAP controller is not fully IEEE
1149.1-compliant.
When the SAMPLE/PRELOAD instruction is loaded in the
instruction register and the TAP controller is in the Capture-DR
state, a snap shot of the data in the device’s input and I/O
buffers is loaded into the boundary scan register. Because the
device system clock(s) are independent from the TAP clock


Similar Part No. - CY7C1363A-117AJC

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1363B CYPRESS-CY7C1363B Datasheet
856Kb / 34P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1363B-100AC CYPRESS-CY7C1363B-100AC Datasheet
856Kb / 34P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1363B-100AI CYPRESS-CY7C1363B-100AI Datasheet
856Kb / 34P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1363B-100AJC CYPRESS-CY7C1363B-100AJC Datasheet
856Kb / 34P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1363B-100AJI CYPRESS-CY7C1363B-100AJI Datasheet
856Kb / 34P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
More results

Similar Description - CY7C1363A-117AJC

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1360A CYPRESS-CY7C1360A Datasheet
558Kb / 28P
   256K x 36/512K x 18 Synchronous Pipelined Burst SRAM
CY7C1355A CYPRESS-CY7C1355A Datasheet
563Kb / 28P
   256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture
logo
GSI Technology
GS881E18 GSI-GS881E18 Datasheet
839Kb / 37P
   512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS88118AT GSI-GS88118AT Datasheet
876Kb / 36P
   512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS880E18AT GSI-GS880E18AT Datasheet
596Kb / 24P
   512K x 18, 256K x 32, 256K x 36 9Mb Synchronous Burst SRAMs
logo
Austin Semiconductor
AS5SS256K36 AUSTIN-AS5SS256K36 Datasheet
332Kb / 16P
   256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM
AS5SS256K36 AUSTIN-AS5SS256K36_05 Datasheet
397Kb / 16P
   256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM
logo
AMIC Technology
A67L93181 AMICC-A67L93181 Datasheet
246Kb / 18P
   512K X 18, 256K X 36 LVTTL, Flow-through ZeBL SRAM
logo
Cypress Semiconductor
CY7C1361B CYPRESS-CY7C1361B Datasheet
856Kb / 34P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
logo
AMIC Technology
A67P93181 AMICC-A67P93181_15 Datasheet
251Kb / 18P
   512K X 18, 256K X 36 LVTTL, Flow-through ZeBL SRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com