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CY7C1339B
Document #: 38-05141 Rev. *A
Page 7 of 17
Write Cycle Descriptions[4, 5, 6]
Function
GW
BWE
BW3
BW2
BW1
BW0
Read
1
1
XX
XX
Read
10
11
11
Write Byte 0 – DQ[7:0]
10
11
10
Write Byte 1 – DQ[15:8]
10
11
01
Write Bytes 1, 0
1
01
10
0
Write Byte 2 – DQ[23:16]
10
10
11
Write Bytes 2, 0
1
01
01
0
Write Bytes 2, 1
1
01
00
1
Write Bytes 2, 1, 0
1
0
1
0
0
0
Write Byte 3 – DQ[31:24]
10
01
11
Write Bytes 3, 0
1
00
11
0
Write Bytes 3, 1
1
00
10
1
Write Bytes 3, 1, 0
1
0
0
1
0
0
Write Bytes 3, 2
1
00
01
1
Write Bytes 3, 2, 0
1
0
0
0
1
0
Write Bytes 3, 2, 1
1
0
0
0
0
1
Write All Bytes
1
0
0
0
0
0
Write All Bytes
0
X
X
X
X
X
Notes:
4.
X = “don't care,” 1 = Logic HIGH, 0 = Logic LOW.
5.
The SRAM always initiates a Read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW[3:0]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state. OE
is a don't care for the remainder of the Write cycle.
6.
OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQ = High-Z when OE is inactive
or when the device is deselected, and DQ = data when OE is active.
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