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74ALS651-1D Datasheet(PDF) 5 Page - NXP Semiconductors |
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74ALS651-1D Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 13 page Philips Semiconductors Product specification 74ALS651/74ALS651-1 74ALS652/74ALS652-1 Transceiver/register 1991 Feb 08 5 LOGIC DIAGRAM – 74ALS651/651-1 VCC = Pin 24 GND = Pin 12 A0 OEBA B0 1D C1 1D C1 1 OF 8 CHANNELS TO 7 OTHER CHANNELS 21 4 20 3 23 22 1 2 OEAB CPBA SBA SPAB SAB SC00134 LOGIC DIAGRAM – 74ALS652/652-1 VCC = Pin 24 GND = Pin 12 A0 OEBA B0 1D C1 1D C1 1 OF 8 CHANNELS TO 7 OTHER CHANNELS 21 4 20 3 23 22 1 2 OEAB CPBA SBA SPAB SAB SC00135 FUNCTION TABLE INPUTS DATA I/O OPERATING MODE OEAB OEBA CPAB CPBA SAB SBA An Bn 74ALS651/74ALS651-1 74ALS652/74ALS652-1 L H H or L H or L X X Input Input Isolation Isolation L H ↑ ↑ X X Input Input Store A and B data Store A and B data X H ↑ H or L X X Input Unspecified* Store A, hold B Store A, hold B H H ↑ ↑ L X Input Output Store A in both registers Store A in both registers L X H or L ↑ X S Unspecified* Input Hold A, store B Hold A, store B L L ↑ ↑ X L Output Input Store B in both registers Store B in both registers L L X X X L Output Input Real time B data to A bus Real time B data to A bus L L X H or L X H Output Input Stored B data to A bus Stored B data to A bus H H X X L X Input Output Real time A data to B bus Real time A data to B bus H H H or L X H X Input Output Stored A data to B bus Stored A data to B bus H L H or L H or L H H Output Output Stored A data to B bus Stored A data to B bus H L H or L H or L H H Output Output Stored B data to A bus Stored B data to A bus NOTES: H = High voltage level L = Low voltage level X = Don’t care * = The data output function may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock. ↑ = Low-to-High clock transition |
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