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SAB-C161CS-LF Datasheet(PDF) 9 Page - Infineon Technologies AG |
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SAB-C161CS-LF Datasheet(HTML) 9 Page - Infineon Technologies AG |
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9 / 89 page  C161CS/JC/JI-32R C161CS/JC/JI-L Data Sheet 5 V3.0, 2001-01 Table 2 Pin Definitions and Functions Symbol Pin No. Input Outp. Function RST OUT 1 O Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. NMI 2 I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C161CS/JC/JI to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. P6 P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7 5 6 7 8 9 10 11 12 IO O O O O O I I/O O Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. Port 6 outputs can be configured as push/ pull or open drain drivers. The Port 6 pins also serve for alternate functions: CS0 Chip Select 0 Output CS1 Chip Select 1 Output CS2 Chip Select 2 Output CS3 Chip Select 3 Output CS4 Chip Select 4 Output HOLD External Master Hold Request Input HLDA Hold Acknowledge Output (master mode) or Input (slave mode) BREQ Bus Request Output |
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