1Mx36 & 2Mx18 Synchronous SRAM

- 11 -

K7A321830C

K7A323630C

Preliminary

Rev. 0.2 April 2006

AC TIING CHARACTERISTICS

Notes : 1. The above parameters are also guaranteed at industrial temperature range.

2. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS

is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.

3. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.

4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.

Parameter

Symbol

-20

Unit

MIN

MAX

Cycle Time

5.0

-

ns

Clock Access Time

-3.1

ns

Output Enable to Data Valid

-3.1

ns

Clock High to Output Low-Z

0-

ns

Output Hold from Clock High

1.5

-

ns

Output Enable Low to Output Low-Z

0-

ns

Output Enable High to Output High-Z

-3.0

ns

Clock High to Output High-Z

1.5

3.0

ns

Clock High Pulse Width

2.0

-

ns

Clock Low Pulse Width

2.0

-

ns

Address Setup to Clock High

1.4

-

ns

Address Status Setup to Clock High

1.4

-ns

Data Setup to Clock High

1.4

-ns

1.4

-ns

Address Advance Setup to Clock High

1.4

-

ns

Chip Select Setup to Clock High

1.4

-

ns

Address Hold from Clock High

0.4

-

ns

Address Status Hold from Clock High

0.4

-

ns

Data Hold from Clock High

0.4

-

ns

0.4

-

ns

Address Advance Hold from Clock High

0.4

-

ns

Chip Select Hold from Clock High

0.4

-

ns

ZZ High to Power Down

2

-

cycle

ZZ Low to Power Up

2

-

cycle