SN65LVCP23

SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004

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8

EN

3 V

1.5 V

0 V

0 V

tPHKL

tPKLH

OUT+

OUT−

1 pF

VOUT+

VOUT−

1 V or 1.4 V

1.2 V

EN

50

Ω

VTT

50

Ω

VTT

+VOD

−VOD

Vdiff = (OUT+) − (OUT−)

NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse-repetition rate (PRR) = 0.5 Mpps, pulse

width = 500

± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.

Figure 4. Enable and Disable Time Circuit and Definitions

Table 1. Receiver Input Voltage Threshold Test

APPLIED VOLTAGES

RESULTING DIFFERENTIAL

INPUT VOLTAGE

RESULTING COMMON-

MODE INPUT VOLTAGE

OUTPUT

VIA

VIB

VID

VIC

1.25 V

1.15 V

100 mV

1.2 V

H

1.15 V

1.25 V

−100 mV

1.2 V

L

4.0 V

3.9 V

100 mV

3.95 V

H

3.9 V

4. 0 V

−100 mV

3.95 V

L

0.1 V

0.0 V

100 mV

0.05 V

H

0.0 V

0.1 V

−100 mV

0.05 V

L

1.7 V

0.7 V

1000 mV

1.2 V

H

0.7 V

1.7 V

−1000 mV

1.2 V

L

4.0 V

3.0 V

1000 mV

3.5 V

H

3.0 V

4.0 V

−1000 mV

3.5 V

L

1.0 V

0.0 V

1000 mV

0.5 V

H

0.0 V

1.0 V

−1000 mV

0.5 V

L

H = high level, L = low level