 |
 |
|
| 74ALS112A |
|
|||||||||||||||||
 PHILIPS
|
| |||||||||||||||||
|
3 page 
Philips Semiconductors Product specification 74ALS112A Dual J-K negative edge-triggered flip-flop 1996 Jun 27 3 LOGIC DIAGRAM 5, 9 4, 10 2, 12 1, 13 6, 7 15, 14 3, 11 Qn SDn Kn Qn RDn Jn CPn SF00106 VCC = Pin 16 GND = Pin 8 FUNCTION TABLE INPUTS OUTPUTS OPERATING MODE SD RD CP J K Q Q OPERATING MODE L H X X X H L Asynchronous Set H L X X X L H Asynchronous Reset L L X X X H* H* Undetermined * H H ↓ h h q q Toggle H H ↓ h l H L Load “1” (Set) H H ↓ l h L H Load “0” (Reset) H H ↓ l l q q Hold “no change” H H H X X q q Hold “no change” H = High voltage level h = High state must be present one setup time prior to High-to-Low clock transition L = Low voltage level l = Low state must be present one setup time prior to High-to-Low clock transition q = Lower case indicate the state of the referenced output prior to the High-to-Low clock transition X = Don’t care ↓ = High-to-Low clock transition * = Both outputs will be High while both SD and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously Asynchronous inputs: Low input to SD sets Q to High level, Low input to RD sets Q to Low level. Set and reset are independent of clock. Simultaneous Low on both SD and RD makes both Q and Q High. |
