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MPC823PAD Datasheet(PDF) 4 Page - Motorola, Inc |
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MPC823PAD Datasheet(HTML) 4 Page - Motorola, Inc |
4 / 12 page 4 MPC823e Mobile Computing Microprocessor MOTOROLA • Serial Interface with the Two Time-Slot Assigners — Allows Serial Communication Controllers and Serial Management Controllers to be Used in Multiplexed and/or Nonmultiplexed Operation — Supports T1, CEPT, PCM Highway, ISDN Basic Rate, ISDN Primary Rate, User-Defined — 1- or 8-Bit Resolution — Allows Independent Transmit and Receive Routing, Frame Syncs, and Clocking — Allows Dynamic Changes — Can be Internally Connected to Four Serial Channels • General-Purpose Timers — Four 16-Bit Timers or Two 32-Bit Timers — Gate Mode Can Enable/Disable Counting — Interrupt can be Masked on Reference Match and Event Capture • Interrupts — Seven External Interrupt Request (IRQ) Lines — One Nonmaskable Interrupt — Twelve Port Pins with Interrupt Capability — Ten Internal Interrupt Sources — Programmable Highest Priority Request • Memory Controller (Eight Banks) — Can be Programmed to Support Almost any Memory Interface — Each Bank Can be a Chip-Select or RAS to Support a DRAM Bank — A Maximum of 30 Wait States per Memory Bank Can be Programmed — Glueless Interface to DRAM Single In-Line Memory Modules, Static RAM, Electrically Programmable Read-Only Memory, Flash EPROM, or Synchronous DRAM — Four CAS Lines, Four WE Lines, and One OE Line — Boot Chip-Select Available at Reset (Options for 8-, 16-, or 32-Bit Memory) — Variable Block Sizes—32K to 256M — Selectable Write Protection — On-Chip Bus Arbitration Supports External Bus Master — Special Features for Burst Mode Support • System Integration Unit — Hardware Bus Monitor — Spurious Interrupt Monitor — Software Watchdog Timer — Periodic Interrupt Timer — Low-Power Stop Mode — Clock Synthesizer — PowerPC Decrementer and Timebase — Real-Time Clock — Reset Controller — IEEE 1149.1 Test Access Port (JTAG) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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