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74AHC1G07 Datasheet(PDF) 8 Page - NXP Semiconductors |
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74AHC1G07 Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 16 page 2002 Oct 02 8 Philips Semiconductors Product specification Buffer with open-drain output 74AHC1G07; 74AHCT1G07 AC WAVEFORMS handbook, full pagewidth MNA592 tPLZ VOL + 0.3 V A input Y output VI VCC VM (1) VOL GND tPZL VM (2) Fig.5 The input A to output Y propagation delays. FAMILY VI INPUT REQUIREMENTS VM(1) INPUT VM(2) OUTPUT AHC1G GND to VCC 50% VCC 50% VCC AHCT1G GND to 3.0 V 1.5 V 50% VCC handbook, full pagewidth open GND VCC VCC VI VO MNA232 D.U.T. CL RT RL = 1000 Ω PULSE GENERATOR S1 Fig.6 Load circuitry for switching times. TEST S1 tPLH/tPHL open tPLZ/tPZL VCC tPHZ/tPZH GND Definitions for test circuit: CL = Load capacitance including jig and probe capacitance (see Chapter “AC characteristics”). RT = Termination resistance should be equal to the output impedance Z0 of the pulse generator. |
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