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MAX9401EHJ Datasheet(PDF) 4 Page - Maxim Integrated Products |
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MAX9401EHJ Datasheet(HTML) 4 Page - Maxim Integrated Products |
4 / 13 page Quad ECL/PECL Differential Buffers/Receivers 4 _______________________________________________________________________________________ Typical Operating Characteristics (Outputs terminated with 50 Ω to VCC - 3.3V, VCC - VEE = +3.3V, VIHD = VCC - 0.9V, VILD = VCC - 1.7V, output is enabled, SEL = high, SEL = low, input transition time = 125ps (20% to 80%), fCLK = 3.0GHz, fIN = 1.5GHz, TA = +25°C, unless otherwise noted.) 70 76 88 82 94 100 -40 10 -15 35 60 85 SUPPLY CURRENT vs. TEMPERATURE TEMPERATURE ( °C) OUTPUTS ARE OPEN; INPUTS ARE HIGH OR LOW 1.6 1.2 0.8 0.4 0 0 1.5 0.5 1.0 2.0 2.5 3.0 DIFFERENTIAL OUTPUT VOLTAGE (VOH - VOL) vs. IN_ FREQUENCY IN_ FREQUENCY (GHz) 100 106 118 112 124 130 -40 10 -15 35 60 85 TRANSITION TIME vs. TEMPERATURE TEMPERATURE ( °C) tR tF 300 380 540 460 620 700 -40 10 -15 35 60 85 PROPAGATION DELAY vs. TEMPERATURE TEMPERATURE ( °C) IN-TO-OUT DELAY CLK-TO-OUT DELAY PIN NAME FUNCTION 1, 8, 11, 17, 24, 30 VCC Positive Supply Voltage. Bypass VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. 2 SEL Noninverting Differential Select Input. Setting SEL = high and SEL = low (differential high) enables all four channels to operate asynchronously. Setting SEL = low and SEL = high (differential low) enables all four channels to operate in synchronized mode. 3 SEL Inverting Differential Select Input 4 CLK Inverting Differential Clock Input. A rising edge on CLK (and falling on CLK) transfers data from the inputs to the outputs when SEL = low. 5 CLK Noninverting Differential Clock Input Pin Description |
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