150mA USB LDO Regulators with ±15kV TVS

and µP Reset

6

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Pin Description

PIN

NAME

DESCRIPTION

1IN

Regulator Input. Supply voltage ranges from +4.0V to +5.5V. Bypass with a 1

µF ceramic capacitor

to ground.

2D+

D+ ESD/Transient Suppression Input. Connect directly to USB port D+ data input. SELR high and

ENR low connects D+ to OUT through a 1.5k

Ω resistor.

3, 9

GND

Ground. This pin also functions as a heatsink. Solder to large pads or the circuit board ground

plane to maximize thermal dissipation.

4D-

D- ESD/Transient Suppression Input. Connect directly to USB port D- data input. SELR low and

ENR low connects D- to OUT through a 1.5k

Ω resistor.

5

SELR

USB Full-Speed/Low-Speed Termination Resistor Select. Logic high connects the termination

resistor to D+ for full-speed peripherals. Logic low connects the termination resistor to D- for low-

speed peripherals. An internal 1.5k

Ω resistor connects to OUT when ENR is low.

6

ENR

USB Termination Resistor Enable. When reset is not asserted, ENR low enables the termination

resistor connection. ENR high or a reset disables the termination resistor connection.

RESET

is held low. RESET remains low for the duration of the reset timeout period after the reset conditions

are terminated. (MAX5005/MAX5006 ONLY)

7

RESET

is held low. RESET remains high for the duration of the reset timeout period after the reset

conditions are terminated. (MAX5007 ONLY)

8

MR

Active-Low Manual Reset Input. A logic low forces a reset. Reset remains asserted for the duration

of the reset timeout period after MR transitions from low to high. Leave unconnected or connect to

OUT if not used. MR has an internal pullup resistor of 25k

Ω to OUT.

10

OUT

Voltage Regulator Output. Fixed +3.3V. Sources up to 150mA. Bypass with a 1

µF (min) capacitor

for full rated performance.