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74ABTL3205 Datasheet(PDF) 8 Page - NXP Semiconductors |
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74ABTL3205 Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 14 page Philips Semiconductors Product specification 74ABTL3205 10-bit BTL transceiver with registers 1995 Jun 16 8 LIVE INSERTION SPECIFICATIONS SYMBOL PARAMETER LIMITS UNIT SYMBOL PARAMETER MIN NOM MAX UNIT VBIASV Bias pin DC current VCC = 0 to 5.25V, Bn = 0 to 2.0 V 4.5 5.5 V IBIASV Bias pin DC current VCC = 0 to 4.75 V, Bn = 0 to 2.0V, Bias V = 4.5 to 5.5V 1 mA IBIASV Bias in DC current VCC = 4.5 to 5.5V, Bn = 0 to 2.0 V, Bias V = 4.5 to 5.5V 10 µA Bn Bus voltage during prebias B0 – B8 = 0V, Bias V = 5.0V 1.62 2.1 V AC ELECTRICAL CHARACTERISTICS A PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C VCC = 5V CL = 50pF, CL = 500Ω Tamb = –40°C to +85°C VCC = 5V ± 10% CL = 50pF, CL = 500Ω UNIT MIN TYP MAX MIN MAX tPLH Propagation delay Waveform 2 2.0 3.6 6.5 2.0 7.3 ns tPHL gy Bn to An Waveform 2 1.8 3.5 6.1 1.8 6.7 ns tPLH Propagation delay, Waveform 2 2.0 3.8 6.5 2.0 7.3 ns tPHL gy BCLK1 to ACLK1 Waveform 2 1.8 3.6 6.1 1.8 6.7 ns tPLH Propagation delay Waveform 2 2.0 3.7 6.5 2.0 7.3 ns tPHL gy BCLK1 to ACLKin Waveform 2 1.8 3.7 6.1 1.8 6.7 ns tPLH Propagation delay Waveform 2 2.0 3.7 6.5 2.0 7.3 ns tPHL gy BCLK2 to ACLK2 Waveform 2 1.8 3.9 6.1 1.8 6.7 ns tPLH Propagation delay Waveform 2 2.0 3.8 6.5 2.0 7.3 ns tPHL gy BCLK2 to AFP Waveform 2 1.8 3.9 6.1 1.8 6.7 ns tPZH Output Enable time Waveform 1 2 2.0 3.8 6.5 2.0 7.3 ns tPLZ OEA1, OEA2, IEA to An Waveform 1, 2 1.8 2.5 6.1 1.8 6.7 ns tPHZ Output Disable time Waveform 4 5 1.6 2.5 5.6 1.4 5.7 ns tPLZ OEA1, OEA2, IEA to An Waveform 4, 5 2.0 3.3 7.8 1.8 8.2 ns tTLH tTHL Output transition time, An Port 10% to 90%, 90% to 10% Test Circuit and Waveforms 3.0 1.7 7.0 4.0 ns tSK(p) Pulse skew2 |tPHL – tPLH| MAX Waveform 3 2.0 ns NOTES: 1. | tPN actual – tPM actual | for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). 2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle. (50MHz input frequency and 50% duty cycle, tested on data paths only). |
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