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74ABT899A Datasheet(PDF) 2 Page - NXP Semiconductors |
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74ABT899A Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 16 page Philips Semiconductors Product specification 74ABT899 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State) 2 1998 Jan 16 853-1623 18864 FEATURES • Symmetrical (A and B bus functions are identical) • Selectable generate parity or ”feed-through” parity for A-to-B and B-to-A directions • Independent transparent latches for A-to-B and B-to-A directions • Selectable ODD/EVEN parity • Continuously checks parity of both A bus and B bus latches as ERRA and ERRB • Ability to simultaneously generate and check parity • Can simultaneously read/latch A and B bus data • Output capability: +64 mA/–32mA • Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17 • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model • Power up 3-State • Power-up reset • Live insertion/extraction permitted DESCRIPTION The 74ABT899 is a 9-bit to 9-bit parity transceiver with separate transparent latches for the A bus and B bus. Either bus can generate or check parity. The parity bit can be fed-through with no change or the generated parity can be substituted with the SEL input. Parity error checking of the A and B bus latches is continuously provided with ERRA and ERRB, even with both buses in 3-State. The 74ABT899 features independent latch enables for the A and B bus latches, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity. FUNCTIONAL DESCRIPTION The 74ABT899 has three principal modes of operation which are outlined below. All modes apply to both the A-to-B and B-to-A directions. Transparent latch, Generate parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are High and the Mode Select (SEL) is Low, the parity generated from A0-A7 and B0-B7 can be checked and monitored by ERRA and ERRB. (Fault detection on both input and output buses.) Transparent latch, Feed-through parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is High. Parity is still generated and checked as ERRA and ERRB and can be used as an interrupt to signal a data/parity bit error to the CPU. Latched input, Generate/Feed-through parity, Check A (and B) bus parity: Independent latch enables (LEA and LEB) allow other permutations of: • Transparent latch / 1 bus latched / both buses latched • Feed-through parity / generate parity • Check in bus parity / check out bus parity / check in and out bus parity QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Tamb = 25°C; GND = 0V TYPICAL UNIT tPLH tPHL Propagation delay An to Bn or Bn to An CL = 50pF; VCC = 5V 2.9 ns tPLH tPHL Propagation delay An to ERRA CL = 50pF; VCC = 5V 6.1 ns CIN Input capacitance VI = 0V or VCC 4 pF CI/O Output capacitance Outputs disabled; VO = 0V or VCC 7 pF ICCZ Total supply current Outputs disabled; VCC =5.5V 50 µA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 28-Pin Plastic PLCC –40 °C to +85°C 74ABT899 A 74ABT899 A SOT261-3 28-Pin Plastic SOP –40 °C to +85°C 74ABT899 D 74ABT899 D SOT136-1 28-Pin Plastic SSOP –40 °C to +85°C 74ABT899 DB 74ABT899 DB SOT341-1 |
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