4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36

ADVANCE

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54W2MH18B_A.fm - Rev 9/02

11

©2002, Micron Technology Inc.

Figure 4

Bus Cycle State Diagram

NOTE:

1. The address is concatenated with one additional internal LSB to facilitate burst operation. The address order is always fixed as xxx .

. . xxx + 0, xxx . . . xxx + 1. Bus cycle is terminated at the end of this sequence (burst count = 2).

2. State transitions: RD = (R# = LOW); WT = (W# = LOW).

3. Read and write state machines can be simultaneously active.

4. State machine control timing sequence is controlled by K.

LOAD NEW

READ ADDRESS

READ DOUBLE

POWER-UP

Supply voltage

provided

READ PORT NOP

R_Init=0

RD

RD

always

/RD

/RD

LOAD NEW

WRITE ADDRESS

AT K#

↑

WRITE DOUBLE

AT K#

↑

Supply voltage

provided

WRITE PORT NOP

WT

WT

always

/WT

/WT