LX1695

Microsemi

Integrated Products Division

11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570

Page 2

Switched Royer CCFL Inverter Monitor IC

Copyright

© 2004

Rev. 1.0a, 2006-01-06

TM

®

ABSOLUTE MAXIMUM RATINGS

Output Current (ROYER) ...........................................................................150mA

RoHS / Pb-free Peak Package Solder Reflow Temperature

(40 seconds Maximum Exposure) .....................................................................................260°C (+0, -5)

Note: Exceeding these ratings could cause damage to the device. All voltages are with respect to

Ground. Currents are positive into, negative out of specified terminal

.

TH ERMAL DATA

M

Plastic 8-Pin DIP

THERMAL RESISTANCE

θ

JA

85

°C/W

THERMAL RESISTANCE

θ

JA

163

°C/W

The

above assume no ambient airflow.

PACKAGE PIN OUT

1

2

3

4

5

6

7

8

DIM_FREQ

ENABLE

FLT_DLY

BRITE_IN

OLSNS

GND

ROYER

VDD

DM Package

(Top View)

1

2

3

45

6

7

8

DIM_FREQ

ENABLE

FLT_DLY

BRITE_IN

VDD

ROYER

GND

OLSNS

M Package

(Top View)

RoHS / Pb-free 100% Matte Tin Lead Finish

FUNCTIONAL PIN DESCRIPTION

Name

Description

VDD

GND

Ground

BRITE_IN

Lamp Brightness Control. A DC input of 0 to 2V controls the duty cycle of the Royer output. Zero volts

corresponds to minimum duty cycle (3.125%), maximum input voltage must yield 100% duty cycle. BRITE_IN

has a high input impedance.

OL_SNS

Open Lamp Sense Input. This input receives rectified and filtered voltages from each Royer transformer

secondary winding that are proportional to lamp current amplitude. These signals are diode OR’ed and

compared to 3VDC at the OL_SNS input. If an under limit condition is detected, a fault is declared and the output

is turned off. This condition is latched and can only be cleared by cycling the main power input or the ENABLE

input signal off and on.

ROYER

Royer Bias Drive Output. This output signal drives external transistors that feed bias currents to one or more

oscillators to turn them on. Output drive is totem pole and must be capable of ±50mA at 0.4 and 4.0V output

when the supply voltage is 4.5 to 5.5 volts.

FLT_DLY

Fault Delay. An external resistor and capacitor at this pin program the time that open lamp fault detection is

disabled following power on or an ENABLE low to high transition. By choosing the appropriate resistor and

capacitor combination, delay time may be as high as 5 seconds

DIM_FREQ

A resistor to ground determines the frequency of the dual slope ramp generator for the digital dimming PWM.

This pin may be overdriven through a resistor with totem pole output logic gates to force an external clock to over

ride the internal clock, allowing the ROYER output to be synchronized to an external frequency without using

another package pin. Input voltage levels of the external pulse are as follows:

High state is; 2.9 to 5.5V minus 0.4 volts noise margin for minimum of 2.5 volts.

Low state is; 0 to 0.36V plus 0.44 volts for noise margin for total of 0.8 volts.

ENABLE

A positive logic level enables the ROYER output pin. A low level turns it off, resets the fault latch and discharges

the FLT_DLY capacitor. Logic threshold is about 1.6V. Upon ENABLE going high (True), the fault delay

capacitor is allowed to charge, initiating the delay.