First Write

First Read

Burst Write

Burst Read

Deselect

R

W

CR

CW

X

X

WR

R

W

R

X

X

X

CR

R

CW

CR

CR

W

CW

W

CW

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

GS816272C

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 2.18 11/2005

8/31

© 1999, GSI Technology

Simplified State Diagram with G