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GS88037BT-V Datasheet(PDF) 1 Page - GSI Technology |
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GS88037BT-V Datasheet(HTML) 1 Page - GSI Technology |
1 / 19 page GS88037BT-xxxV 256K x 36 9Mb Sync Burst SRAM 250 MHz–200 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O 100-Pin TQFP Commercial Temp Industrial Temp Rev: 1.03 6/2006 1/19 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Features • Single Cycle Deselect (SCD) operation • 1.8 V or 2.5 V +10%/–10% core power supply • 1.8 V or 2.5 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 100-lead TQFP package • RoHS-compliant 100-lead TQFP package available Functional Description Applications The GS88037BT-xxxV is a 9,437,184-bit (8,388,608-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. SCD Pipelined Reads The GS88037BT-xxxV is a SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS88037BT-xxxV operates on a 1.8 V or 2.5 V power supply. All input are 2.5 V and 1.8 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 2.5 V and 1.8 V compatible. Parameter Synopsis -250 -200 Unit Pipeline 3-1-1-1 tKQ tCycle 2.5 4.0 2.5 5.0 ns ns Curr (x36) 330 270 mA |
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