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GS8342S09E-333I Datasheet(PDF) 11 Page - GSI Technology |
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GS8342S09E-333I Datasheet(HTML) 11 Page - GSI Technology |
11 / 39 page Preliminary GS8342S08/09/18/36E-333/300/250/200/167 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.02 8/2005 11/39 © 2003, GSI Technology FLXDrive-II Output Driver Impedance Control HSTL I/O SigmaSIO-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a vendor-specified tolerance is between 150 Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature every 1024 cycles. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. Impedance updates for “0s” occur whenever the SRAM is driving “1s” for the same DQs (and vice-versa for “1s”) or the SRAM is in HI-Z. Separate I/O Burst of 2 Sigma SIO-II SRAM Truth Table A LD R/W Current Operation D D Q Q K ↑ (tn) K ↑ (tn) K ↑ (tn) K ↑ (tn) K ↑ (tn+1) K ↑ (tn+1) K ↑ (tn+1) K ↑ (tn+1) X 1 X Deselect X — Hi-Z — V 0 1 Read X — Q0 Q1 V 0 0 Write D0 D1 Hi-Z — Notes: 1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care” 2. “—” indicates that the input requirement or output state is determined by the next operation. 3. Q0 and Q1 indicate the first and second pieces of output data transferred during Read operations. 4. D0 and D1 indicate the first and second pieces of input data transferred during Write operations. 5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when pre- ceded by a Read command. 6. CQ is never tristated. 7. Users should not clock in metastable addresses. |
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