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GS8182S18D-267 Datasheet(PDF) 8 Page - GSI Technology |
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GS8182S18D-267 Datasheet(HTML) 8 Page - GSI Technology |
8 / 31 page GS8182S18D-267/250/200/167 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.08a 8/2005 8/31 © 2003, GSI Technology Burst of 2 SigmaSIO-II SRAM Depth Expansion Write A Read B Write C Read D Write E Read F Read G Read H NOP A B C D E F G H A A+1 E E+1 C C+1 A A+1 E E+1 C C+1 D D+1 G B B+1 F F+1 K K Address LD(Bank_1) LD(Bank_2) R/W(Bank_1) R/W(Bank_2) BWx(Bank_1) BWx(Bank_2) D(Bank_1) D(Bank_2) C(Bank_1) C(Bank_1) Q(Bank_1) CQ(Bank)1 CQ(Bank_1) C(Bank_2) C(Bank_2) Q(Bank_2) CQ(Bank_2) CQ(Bank_2) FLXDrive-II Output Driver Impedance Control HSTL I/O SigmaSIO-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a vendor-specified tolerance is between 150 Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature every 1024 cycles. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. |
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